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ORCIDJing Jin 0005
Person information
- affiliation: Shanghai Jiao Tong University, School of Microelectronics, China
Other persons with the same name
- Jing Jin — disambiguation page
- Jing Jin 0001
![[0000-0002-6133-5491]](http://222.178.203.72:19005/whst/63/=cakoznqf//img/orcid-mark.12x12.png "0000-0002-6133-5491")
— East China University of Science and Technology, Key Lab. of Advanced Control and Optimization for Chemical Processes, Shanghai, China - Jing Jin 0002 — Nanjing University, School of Electronic Science and Engineering, Jiangsu, China
- Jing Jin 0003 — Harbin Institute of Technology, School of Astronautics, China
- Jing Jin 0004 — Nanyang Technological University, Singapore, Singapore
- Jing Jin 0006 — City University of Hong Kong, Hong Kong
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2020 – today
- 2025
[j28]Zhaolin Yang, Xiaoming Liu, Jing Jin, Jianjun Zhou:
A reconfigurable passive LNA using an N-path switched-capacitor transformer with 2×/3× voltage Gain. Microelectron. J. 156: 106541 (2025)- [j27]Zhaolin Yang, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 234-247 (2025) - 2024
- [j26]Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jing Jin, Jun Yang, Mingoo Seok:
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core. IEEE J. Solid State Circuits 59(2): 605-615 (2024) - [j25]Xiaofei Wang, Jing Jin, Xiaoming Liu, Hui Wang, Huzhi Tang, Chao Yang, Yuekang Guo, Tingting Mo, Jianjun Zhou:
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 560-572 (2024) - [c42]Runtao Huo, Dingguo Zhang, Jing Jin, Jianjun Zhou, Hui Wang:
A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique. CICC 2024: 1-2 - [c41]Jing Jin, Yuekang Guo, Meng Xu, Xiaoming Liu, Nan Sun, Jianjun Zhou:
A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer. CICC 2024: 1-2 - [c40]Zhengyuan Lou, Meng Xu, Yuekang Guo, Jing Jin, Jianjun Zhou:
A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC. ISCAS 2024: 1-5 - [c39]Tong Zhang, Dingguo Zhang, Jing Jin, Patrick P. Mercier, Hui Wang:
Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor. ISCAS 2024: 1-5 - 2023
- [j24]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. IEEE J. Solid State Circuits 58(2): 474-485 (2023) - [j23]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization. IEEE J. Solid State Circuits 58(9): 2554-2563 (2023) - [j22]Chao Yang, Sheng Wang, Xiaoming Liu, Jing Jin, Jianjun Zhou:
A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS. Microelectron. J. 139: 105890 (2023) - [j21]Minjing Lee, Xiaoming Liu, Zhaolin Yang, Jing Jin, Lin-Sheng Wu:
A Compact 0.2-1.6 GHz 20 MHz-Bandwidth Passive-LNA Exploiting an N-Path 1:3 Transformer. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1699-1703 (2023) - [c38]Hanqi Gao, Jing Jin, Zhaolin Yang, Jianjun Zhou, Xiaoming Liu:
A 30GHz Bidirectional PA/LNA with Transformer-Based Switchable RC Matching Network. ASICON 2023: 1-4 - [c37]Zhaolin Yang, Jing Jin, Yuyang Chen, Jianjun Zhou, Xiaoming Liu:
A Wideband Inductorless LNA Employing Dual-Loop Feedback for Low-Power Applications. ASICON 2023: 1-4 - [c36]Jiaxu Zhou, Jing Jin, Yichao Lin, Shan Wang, Bo Wang, Tingting Mo:
A 24/48 Gb/s NRZ/PAM-4 Dual-Mode Transmitter with 3-tap FFE in 28 nm CMOS. ASICON 2023: 1-4 - [c35]Shengyuan Zhou, Ziyao Xia, Chao Yang, Xiaoming Liu, Sheng Wang, Jing Jin:
Fast locking Sampling PLL Using Phase Error Eliminator. ASICON 2023: 1-4 - [c34]Yuekang Guo, Jing Jin, Xiaoming Liu, Zhaolin Yang, Jianjun Zhou:
A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$. ISCAS 2023: 1-4 - [c33]Huzhi Tang, Xiaoming Liu, Chao Yang, Jing Jin:
An ADPLL with Two-Point Modulation Gain Calibration for 2.4GHz ISM-Band in 40nm CMOS. ISCAS 2023: 1-4 - [c32]Xiaofei Wang, Jing Jin, Xiaoming Liu, Zhaolin Yang, Shan Wang, Jianjun Zhou:
A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces. ISCAS 2023: 1-4 - [c31]Jiayi Chen, Xiaoming Liu, Chao Yang, Jing Jin, Zhongyuan Chang, Jianjun Zhou:
Predictive LSB-First Successive Approximation for SAR Analog-to-Digital Converters. MWSCAS 2023: 118-122 - [c30]Shunyan Wang, Yuekang Guo, Qiang Pan, Xiaoming Liu, Shan Wang, Jing Jin:
A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration. MWSCAS 2023: 482-485 - [c29]Ke Wu, Yuekang Guo, Xiaoming Liu, Jing Jin, Howard C. Yang, Jianjun Zhou:
A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions. MWSCAS 2023: 609-613 - 2022
- [j20]Ran Bu, Jing Jin, Zhaolin Yang, Yuekang Guo, Jianjun Zhou:
A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique. Circuits Syst. Signal Process. 41(12): 6672-6693 (2022) - [j19]Li Ding, Jing Jin, Jianjun Zhou:
A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(11): 1443-1449 (2022) - [j18]Chao Yang, Xiaoming Liu, Jing Jin, Jianjun Zhou:
A 0.023-12 GHz ultra-wideband frequency synthesizer with FOMT of -251.8 dB. Microelectron. J. 120: 105357 (2022) - [j17]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4787-4798 (2022) - [j16]Chao Yang, Xiaoming Liu, Jing Jin, Yuekang Guo, Jianjun Zhou:
A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 3998-4002 (2022) - [c28]Yuekang Guo, Xiaoming Liu, Jing Jin, Jianjun Zhou:
A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme. ISCAS 2022: 2650-2654 - [c27]Ke Wu, Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration. MWSCAS 2022: 1-4 - 2021
- [j15]Mengying Hu, Jing Jin, Yuekang Guo, Xiaoming Liu, Jianjun Zhou:
A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. Circuits Syst. Signal Process. 40(7): 3125-3142 (2021) - [j14]Haopeng Kang, Jing Jin, Xiaoming Liu, Xiaofei Wang, Pengli Hong, Jianjun Zhou:
A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction. Microelectron. J. 108: 104991 (2021) - [j13]Xiaoming Liu, Jing Jin, Xiaofei Wang, Jianjun Zhou:
A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS. Microelectron. J. 113: 105065 (2021) - [j12]Li Ding, Ke Wu, Jing Jin, Jianjun Zhou:
An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications. Microelectron. J. 117: 105279 (2021) - [c26]Chenyue Shi, Shengyuan Zhou, Jing Jin:
An Enhanced SSCP for Frequency Drift Suppressing in SSPLL. ASICON 2021: 1-4 - [c25]Tao Zhong, Yuekang Guo, Jing Jin:
Analysis of SAR ADC Quantization Error and Nonlinearity in PMCW Automotive Radar. ASICON 2021: 1-4 - [c24]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC. ISCAS 2021: 1-4 - [c23]Zhengqi Xu, Ke Wu, Xiaoming Liu, Chengyuan Liu, Jing Jin, Jianjun Zhou:
A Ka-Band Quadrature-Hybrid LNA-PS with Gm- Boosting Technique in 40-nm CMOS. ISCAS 2021: 1-5 - [c22]Yuekang Guo, Jing Jin, Jianjun Zhou:
A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC. MWSCAS 2021: 18-21 - [c21]Yuekang Guo, Qiang Pan, Xiaoming Liu, Jing Jin:
A Center Frequency Calibration Technique for Ring VCO Exploiting Delay-1 Detection. MWSCAS 2021: 708-711 - [c20]Qiang Pan, Yuekang Guo, Jing Jin, Jianjun Zhou:
A Linearization Technique for Ring VCO Exploiting Bulk-Modulation. MWSCAS 2021: 737-740 - [c19]Yanlin He, Yuekang Guo, Jing Jin, Jianjun Zhou:
A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs. MWSCAS 2021: 941-944 - 2020
- [j11]Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration. IEEE Trans. Circuits Syst. 67-I(11): 3630-3642 (2020) - [j10]Litong Liu, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A Multi-Modulus Fractional Divider With TDC Free Calibration Scheme for Mitigation of TX-VCO Pulling. IEEE Trans. Circuits Syst. 67-II(12): 2848-2852 (2020) - [j9]Xiaofei Wang, Jing Jin, Xiaoming Liu, Jianjun Zhou:
An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance. IEEE Trans. Circuits Syst. 67-II(12): 2898-2902 (2020) - [c18]Tu Hong, Ning Guan, Chen Yin, Qin Wang, Jianfei Jiang, Jing Jin, Guanghui He, Naifeng Jing:
Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. ISCAS 2020: 1-5 - [c17]Ran Wang, Yuekang Guo, Jing Jin, Xiaoming Liu, Naifeng Jing, Jianjun Zhou:
A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j8]Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1623-1627 (2019) - [j7]Jing Jin, Xiaoming Liu, Taotao Yan, Jianjun Zhou:
Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receivers. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1683-1687 (2019) - [j6]Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing:
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. ACM Trans. Design Autom. Electr. Syst. 24(2): 25:1-25:22 (2019) - [c16]Songhao Guo, Li Ding, Jing Jin:
A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration. ASICON 2019: 1-4 - [c15]Yu Ji, Li Ding, Jing Jin:
A High-Linear Digital-to-Phase Converter in 40nm CMOS. ASICON 2019: 1-4 - [c14]Zhigang Li, Xiaofei Wang, Jing Jin:
A 0.0558-mm2 0.05-0.9GHz Low-Power Multi-phase Non-overlap Clock Generator in 40 nm CMOS. ASICON 2019: 1-4 - [c13]Yingying Liang, Xiaoming Liu, Jing Jin:
An Optimized Modeling Method for Transformer Design. ASICON 2019: 1-4 - [c12]Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing:
A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. ISCAS 2019: 1-5 - 2018
- [j5]Rui Guan, Jianfeng Xue, Chao Yang, Jing Jin, Jianjun Zhou:
16-bit 1-MS/s SAR ADC with foreground digital-domain calibration. IET Circuits Devices Syst. 12(4): 505-513 (2018) - [j4]Rui Guan, Jing Jin, Jianjun Zhou:
A low-cost digital-domain foreground calibration for high resolution SAR ADCs. Microelectron. J. 73: 86-93 (2018) - [c11]Heng Liu, Li Ding, Jing Jin, Jianjun Zhou:
A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse. ISCAS 2018: 1-5 - [c10]Hanchun Tang, Li Ding, Jing Jin, Jianjun Zhou:
A 28 Gb/s 2-Tap FFE Source-Series-Terminated Transmitter in 22 nm CMOS FDSOI. ISCAS 2018: 1-4 - 2017
- [c9]Licheng Xu, Xinchi Gao, Jing Jin:
A high-speed low-power charge pump with dynamic current matching. ASICON 2017: 800-803 - [c8]Shaoqin Yao, Litong Liu, Jing Jin:
A passive mixer-first receiver with negative feedback for impedance matching. ASICON 2017: 804-806 - [c7]Xinchi Gao, Licheng Xu, Jing Jin, Naifeng Jing, Jianjun Zhou:
A wideband simplified transformer-based VCO with digital amplitude calibration. MWSCAS 2017: 787-790 - 2016
- [j3]Rui Guan, Jing Jin, Wenjie Pan, Dongpo Chen, Jianjun Zhou:
Wideband dual-mode complementary metal-oxide-semiconductor receiver. IET Circuits Devices Syst. 10(2): 87-93 (2016) - [j2]Zhijian Lu, Jing Jin, Tingting Mo, Jianjun Zhou:
Analysis of Input LCR Matched N-Path Filter. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(6): 795-805 (2016) - 2015
- [c6]Bukun Pan, Jing Jin, Jianjun Zhou:
A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunability. ASICON 2015: 1-4 - 2014
- [c5]Jing Jin, Bukun Pan, Xiaoming Liu, Jianjun Zhou:
Injection-Locking Frequency Divider based dual-modulus prescalers with extended locking range. ISCAS 2014: 502-505 - [c4]Jing Jin, Bukun Pan, Xiaoming Liu, Jianjun Zhou:
Digital spur calibration of multi-modulus fractional frequency LO divider utilizing most correlated comparison algorithm. ISCAS 2014: 742-745 - 2012
- [j1]Jing Jin, Xiaoming Liu, Tingting Mo, Jianjun Zhou:
Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(5): 926-937 (2012) - [c3]Hui Wang, Wufeng Wang, Jing Jin, Dongpo Chen, Jianjun Zhou:
Anti-interference pseudo-differential wideband LNA for DVB-S.2 RF tuners. ISCAS 2012: 2151-2154 - 2011
- [c2]Xiaoming Liu, Jing Jin, Xi Li, Jianjun Zhou:
Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs. ISCAS 2011: 478-481 - [c1]Xiaoming Liu, Jing Jin, Cui Mao, Jianjun Zhou:
Linear range extensible Phase Frequency Detector and Charge Pump for fast frequency acquisition. ISCAS 2011: 985-988
Coauthor Index
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