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2020 – today
- 2021
[j7]Xiaomeng Zhang
, Shuo Li, Ray Siferd, Saiyu Ren:
A 170 MHz to 330 MHz Wideband 90 nm CMOS RC-CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver. Circuits Syst. Signal Process. 40(11): 5249-5263 (2021)
2010 – 2019
- 2019
- [j6]Isaac Abraham, Saiyu Ren, Raymond E. Siferd:
Logistic Function Based Memristor Model With Circuit Application. IEEE Access 7: 166451-166462 (2019) - [j5]N. V. Vijaya Krishna Boppana, Jeevani Kommareddy, Saiyu Ren:
Low-Cost and High-Performance 8 × 8 Booth Multiplier. Circuits Syst. Signal Process. 38(9): 4357-4368 (2019) - [c9]Isaac Abraham, Saiyu Ren:
Memristor based multifunction oscillator. MWSCAS 2019: 1191-1194 - 2018
- [j4]Hao Xue, Saiyu Ren:
Hardware Trojan detection by timing measurement: Theory and implementation. Microelectron. J. 77: 16-25 (2018) - 2016
- [j3]Shuo Li, Xiaomeng Zhang, Saiyu Ren:
High Frequency Unity Gain Buffer in 90-nm CMOS Technology. J. Circuits Syst. Comput. 25(7): 1650071:1-1650071:17 (2016) - [j2]N. V. Vijaya Krishna Boppana, Saiyu Ren:
A Low-Power and Area-Efficient 64-Bit Digital Comparator. J. Circuits Syst. Comput. 25(12): 1650148:1-1650148:15 (2016) - 2015
- [j1]Saiyu Ren, Isaac Abraham, Seng Hong:
A 1-6 GHz analog radio frequency power driver in 90 nm complementary metal-oxide semiconductor technology for wireless applications. Int. J. Circuit Theory Appl. 43(2): 263-276 (2015) - [c8]Dinesh Varma Penumetcha, Jiafeng Xie, Saiyu Ren:
FPGA design space exploration of IDEA cryptography IP core. MWSCAS 2015: 1-4 - [c7]Eswar Raju Suraparaju, Pushpak Vasanth Rayudu Arja, Saiyu Ren:
A 1.1-8.2 GHz tuning range In-phase and Quadrature output DCO design in 90 nm CMOS technology. MWSCAS 2015: 1-4 - 2013
- [c6]Christopher Benedik, Saiyu Ren:
Passive component stacking to aid power supply decoupling. MWSCAS 2013: 201-204 - [c5]Joe Gerhardt, Saiyu Ren:
Digital Down Converter optimization. MWSCAS 2013: 1015-1018 - [c4]Sunny Raj Dommaraju, Saiyu Ren, George Y. Lee:
Design and implementation of a 16-bit flexible ROM-less direct digital synthesizer. MWSCAS 2013: 1350-1353 - 2011
- [c3]Saiyu Ren, Ray Siferd:
CMOS 1.6 GHz Bandwidth 12 Bit Time Interleaved Pipelined ADC. ITNG 2011: 785-790
2000 – 2009
- 2009
- [c2]Saiyu Ren, Ray Siferd:
Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS. SoCC 2009: 35-38 - 2004
- [c1]Saiyu Ren, Ray Siferd, Robert Blumgold:
Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications. SoCC 2004: 45-48
Coauthor Index
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