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2020 – today
- 2021
[c32]Carolina Adaros Boye, Paul Kearney, Mark B. Josephs
, Hans Ulmer:
An Indicators-of-Risk Library for Industrial Network Security. ARES 2021: 134:1-134:9- [c31]Moojan Pordelkhaki, Shereen Fouad, Mark B. Josephs:
Intrusion Detection for Industrial Control Systems by Machine Learning using Privileged Information. ISI 2021: 1-6 - 2020
- [c30]Xiaohu Zhou, Vitor Jesus, Yonghao Wang, Mark B. Josephs:
User-Controlled, Auditable, Cross-Jurisdiction Sharing of Healthcare Data Mediated by a Public Blockchain. TrustCom 2020: 87-96
2010 – 2019
- 2019
- [c29]Carolina Adaros Boye, Paul Kearney, Mark B. Josephs:
Continuous Risk Management for Industrial IoT: A Methodological View. CRiSIS 2019: 34-49 - [c28]Syed Naqvi, Peter Sommer, Mark B. Josephs:
A Research-Led Practice-Driven Digital Forensic Curriculum to Train Next Generation of Cyber Firefighters. EDUCON 2019: 1204-1211 - [c27]Yussuf Ahmed, Syed Naqvi, Mark B. Josephs:
Cybersecurity Metrics for Enhanced Protection of Healthcare IT Systems. ISMICT 2019: 1-9 - [c26]Xiaohu Zhou, Antonio Nehme, Vitor Jesus, Yonghao Wang, Mark B. Josephs, Khaled Mahbub:
Towards Blockchain-Based Auditing of Data Exchanges. SmartBlock 2019: 43-52 - 2018
- [c25]Yussuf Ahmed, Syed Naqvi, Mark B. Josephs:
Aggregation of security metrics for decision making: a reference architecture. ECSA (Companion) 2018: 53:1-53:7 - [c24]Carolina Adaros Boye, Paul Kearney, Mark B. Josephs:
Collective Responsibility and Mutual Coercion in IoT Botnets - A Tragedy of the Commons Problem. ICETE (1) 2018: 636-646 - [c23]Carolina Adaros Boye, Paul Kearney, Mark B. Josephs:
Cyber-Risks in the Industrial Internet of Things (IIoT): Towards a Method for Continuous Assessment. ISC 2018: 502-519
2000 – 2009
- 2007
- [j15]Mark B. Josephs, Hemangee K. Kapoor:
Controllable Delay-Insensitive Processes. Fundam. Informaticae 78(1): 101-130 (2007) - [c22]Mark B. Josephs:
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR. ASYNC 2007: 83-94 - 2006
- [j14]Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey:
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. Fundam. Informaticae 70(1-2): 21-48 (2006) - [c21]Jun Xu, Reza Sotudeh, Mark B. Josephs:
Asynchronous Packet-Switching for Networks-on-Chip. ACSD 2006: 201-207 - 2005
- [c20]Hemangee K. Kapoor, Mark B. Josephs:
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation. ACSD 2005: 58-67 - 2004
- [j13]Hemangee K. Kapoor, Mark B. Josephs:
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench. Inf. Process. Lett. 89(6): 293-296 (2004) - [c19]Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey:
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. ACSD 2004: 89-98 - [c18]Mark B. Josephs:
Models for Data-Flow Sequential Processes. 25 Years Communicating Sequential Processes 2004: 85-97 - [c17]Hemangee K. Kapoor, Mark B. Josephs:
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. DAC 2004: 830-833 - 2003
- [c16]Mark B. Josephs:
An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits. ASYNC 2003: 121-131 - 2002
- [c15]Mark B. Josephs, Dennis P. Furey:
A Programming Approach to the Design of Asynchronous Logic Blocks. Concurrency and Hardware Design 2002: 34-60 - [c14]Igor Lemberski, Mark B. Josephs:
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. PATMOS 2002: 92-100 - 2000
- [c13]Mark B. Josephs, Dennis P. Furey:
Delay-Insensitive Interface Specification and Synthesis. DATE 2000: 169-173
1990 – 1999
- 1999
- [j12]Steven M. Nowick, Mark B. Josephs, Kees van Berkel:
Special Issue On Asynchronous Circuits And Systems. Proc. IEEE 87(2): 219-222 (1999) - [j11]Kees van Berkel, Mark B. Josephs, Steven M. Nowick:
Applications of asynchronous circuits. Proc. IEEE 87(2): 223-233 (1999) - [j10]Mark B. Josephs, Steven M. Nowick, Kees van Berkel:
Modeling and design of asynchronous circuits. Proc. IEEE 87(2): 234-242 (1999) - 1998
- [j9]Mark B. Josephs:
Protocol Specification, Testing and Verification XV, by Piotr Dembinski and Marek Sredniawa (Editors), Chapman and Hall, 1996 (Book Review). Softw. Test. Verification Reliab. 8(1): 49 (1998) - [c12]Mark B. Josephs:
Formal Derivation of a Loadable Asynchronous Counter. MPC 1998: 234-253 - 1997
- [j8]Mark B. Josephs, Andrew M. Bailey:
The Use of SI-Algebra in the Design of Sequencer Circuits. Formal Aspects Comput. 9(4): 395-408 (1997) - 1996
- [j7]Mark B. Josephs, Jelio Todorov Yantchev:
CMOS design of the tree arbiter element. IEEE Trans. Very Large Scale Integr. Syst. 4(4): 472-476 (1996) - [c11]Martin E. Bush, Mark B. Josephs:
Some limitations to speed-independence in asynchronous circuits. ASYNC 1996: 104-111 - 1995
- [c10]Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev:
Low-latency asynchronous FIFO buffers. ASYNC 1995: 24-31 - [c9]Andrew M. Bailey, Mark B. Josephs:
Sequencer circuits for VLSI programming. ASYNC 1995: 82-90 - 1994
- [j6]Iain S. C. Houston, Mark B. Josephs:
Specifying Distributed CICS in Z: Accessing Local and Remote Resources (Short Communication). Formal Aspects Comput. 6(5): 569-579 (1994) - [c8]Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding, Tom Verhoeff:
Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra. ASYNC 1994: 206-215 - 1993
- [c7]Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding:
Normal Form in a Delay-Insensitive Algebra. Asynchronous Design Methodologies 1993: 57-70 - [c6]Mark B. Josephs, Jan Tijmen Udding:
Implementing a Stack as a Delay-insensitive Circuit. Asynchronous Design Methodologies 1993: 123-135 - 1992
- [j5]Mark B. Josephs:
Receptive Process Theory. Acta Informatica 29(1): 17-31 (1992) - [c5]Mark B. Josephs, Rudolf H. Mak, Jan Tijmen Udding, Tom Verhoeff, Jelio Todorov Yantchev:
High-Level Design of an Asynchronous Packet-Routing Chip. Designing Correct Circuits 1992: 261-274 - 1990
- [c4]Mark B. Josephs, Jan Tijmen Udding:
An Algebra for Delay-Insensitive Circuits. CAV 1990: 343-352 - [c3]Mark B. Josephs, Jan Tijmen Udding:
Delay-Insensitive Circuits: An Algebraic Approach to their Design. CONCUR 1990: 342-366 - [c2]Mark B. Josephs, Jan Tijmen Udding:
An Algebra for Delay-Insensitive Circuits. CAV (DIMACS/AMS volume) 1990: 147-176 - [c1]Jifeng He, Mark B. Josephs, Charles Antony Richard Hoare:
A Theory of Synchrony and Asynchrony. Programming Concepts and Methods 1990: 459-478
1980 – 1989
- 1989
- [j4]Mark B. Josephs:
The Semantics of Lazy Functional Languages. Theor. Comput. Sci. 68(1): 105-111 (1989) - 1988
- [j3]Mark B. Josephs:
A State-Based Approach to Communicating Processes. Distributed Comput. 3(1): 9-18 (1988) - [j2]Mark B. Josephs:
The Data Refinement Calculator for Z Specifications. Inf. Process. Lett. 27(1): 29-33 (1988) - 1986
- [b1]Mark B. Josephs:
Functional programming with side-effects. University of Oxford, UK, 1986 - [j1]Mark B. Josephs:
Functional Programming with Side-Effects. Sci. Comput. Program. 7(3): 279-296 (1986)
Coauthor Index
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