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2010 – 2019
- 2018
[j7]Lijing Zhu, Kun Wang, Duan Zhou, Liangkai Liu, Huaxi Gu:
An Optimization Algorithm to Build Low Congestion Multi-Ring Topology for Optical Network-on-Chip. IEICE Trans. Inf. Syst. 101-D(7): 1835-1842 (2018)- [j6]Lulu Li, Xuehong Qiu, Duan Zhou, Jianxian Zhang:
片上网络容错技术研究 (Research on Fault Tolerant Technology for Networks-on-Chip). 计算机科学 45(3): 305-310 (2018) - 2017
- [j5]Lu Liu, Zhangming Zhu, Duan Zhou, Yintang Yang:
A fair arbitration for Network-on-Chip routing with odd-even turn model. Microelectron. J. 64: 1-8 (2017) - 2015
- [j4]Xiaofeng Zhou, Lu Liu, Zhangming Zhu, Duan Zhou:
A Routing Aggregation for Load Balancing Network-on-Chip. J. Circuits Syst. Comput. 24(9): 1550137:1-1550137:15 (2015) - 2014
- [j3]Di Li, Yintang Yang, Duan Zhou, Yani Li, Xiaopeng Wu:
Design of a Fully Integrated 2.4 GHz frequency PLL synthesizer for ZigBee Transceiver Application. J. Circuits Syst. Comput. 23(10) (2014) - 2012
- [j2]Xiang Gao, Yintang Yang, Duan Zhou, Jianxian Zhang, Changchun Chai:
Target Tracking Approximation Algorithms with Particle Filter Optimization and Fault-Tolerant Analysis in Wireless Sensor Networks. J. Networks 7(5): 832-837 (2012) - 2011
- [c3]Yanfei Yang, Yintang Yang, Zhangming Zhu, Duan Zhou:
A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline. ASICON 2011: 633-636 - 2010
- [j1]Xuguang Guan, Zhangming Zhu, Duan Zhou, Yintang Yang:
High Speed Multi-Resource Arbiter with Active Virtual Channel Allocation for Network on Chips. J. Circuits Syst. Comput. 19(7): 1579-1596 (2010)
2000 – 2009
- 2009
- [c2]Xuguang Guan, Duan Zhou, Yintang Yang, Zhangming Zhu:
A GALS Delay-insensitive Self-timed Wrapper for Network on Chips. PACCS 2009: 265-268 - [c1]Xuguang Guan, Duan Zhou, Dan Wang, Yintang Yang, Zhangming Zhu:
A Novel GALS Single-Track Protocol Asynchronous Communication Circuits. PACCS 2009: 269-272
Coauthor Index
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