基于FPGA的LCD1602的流动显示VHDL设计QUARTUS工程文件.zip

基于FPGA的LCD1602的流动显示VHDL设计QUARTUS工程文件 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity LCD1602_Update is Port ( Clk : in STD_LOGIC; Reset : in STD_LOGIC; data_in1: in STD_LOGIC_VECTOR (7 downto 0); data_in2: in STD_LOGIC_VECTOR (7 downto 0); data_in3: in STD_LOGIC_VECTOR (7 downto 0); data_in4: in STD_LOGIC_VECTOR (7 downto 0); data_in5: in STD_LOGIC_VECTOR (7 downto 0); data_in6: in STD_LOGIC_VECTOR (7 downto 0); password_result: in STD_LOGIC_VECTOR (7 downto 0); LCD_DATA : out STD_LOGIC_VECTOR (7 downto 4); LCD_EN : out STD_LOGIC; LCD_RS : out STD_LOGIC; LCD_RW : out STD_LOGIC; back_light:out std_logic ); end LCD1602_Update; architecture Behavioral of LCD1602_Update is Signal Clk_scan : STD_LOGIC := '0'; Signal Clk_100us : STD_LOGIC ; Signal data_out : STD_LOGIC_VECTOR (7 downto 0) ; Type string1 is array(0 to 5) of STD_LOGIC_VECTOR(7 downto 0); -- constant data1 : string1 := (x"48",x"45",x"4c",x"4c",x"4f",x"21"); --"HELLO!" Type State_Display is ( st_disp1,st_disp2,st_disp3,st_disp4,st_disp5, st_disp6,st_disp7,st_disp8,st_disp9,st_disp10, st_disp11,st_disp12,st_disp13,st_disp14,st_disp15, st_disp16,st_disp17,st_disp18,st_disp19,st_disp20, st_disp21 ); Signal Current_Disp : State_Display := st_disp1; begin back_light <= '1'; Proc_CLK_100us:process(Clk) --Frequency division to 10KHz,which is 100us variable cnt_clk : integer