1553B代码 FPGA代码

1553 decoder-encoder Reference Design =============================================================================== File List 1. /1553_enc_dec/docs/1553_enc_dec.doc --> Design document /1553_enc_dec/docs/readme.txt --> Read me file 2. /1553_enc_dec/source/decoder_1553.v --> Decoder source verilog file /1553_enc_dec/source/encoder_1553.v --> Encoder source verilog file 3. /1553_enc_dec/par/EC/decoder_1553.prf --> Decoder Constraint file for place and route /1553_enc_dec/par/EC/encoder_1553.prf --> Encoder Constraint file for place and route /1553_enc_dec/par/EC/decoder_1553.syn --> Decoder Project file for place and route /1553_enc_dec/par/EC/encoder_1553.syn --> Encoder Project file for place and route 4. /1553_enc_dec/simulation/EC/scripts/runsim_1553.do --> Scripts for RTL simulation 5. /1553_enc_dec/synthesis/EC/synplify/decoder_1553.prj --> Decoder Project file for synthesis using synplify /1553_enc_dec/synthesis/EC/synplify/encoder_1553.prj --> Encoder Project file for synthesis using synplify /1553_enc_dec/synthesis/EC/synplify/decoder_1553.sdc --> Decoder Constraint file for synthesis using synplify /1553_enc_dec/synthesis/EC/synplify/encoder_1553.sdc --> Encoder Constraint file for synthesis using synplify 6. /1553_enc_dec/testbench/test_1553.v --> Testbench for simulation Synthesis 1. Launch synplify 2. Correct the source file pathname in the encoder_1553.prj 3. Open project /1553_enc_dec/synthesis/EC/synplify/encoder_1553.prj 4. Click [Run] Place and Route 1. Launch ispLEVER 2. Open project "/1553_enc_dec/par/EC/encoder_1553.syn" 3. Click "Place and Route Trace Report" on right pannel Simulation 1. Launch modelsim oem edition 2. Click [File] --> [Change Directory...] and select "/1553_enc_dec/simulation/EC/scripts" 3. Click [Tools] --> [Excute Macro] simulation, select "/1553_enc_dec/simulation/EC/scripts/runsim_1553.do"