library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY decode4-16 IS
PORT(a,b,c,d:IN STD_LOGIC;
q:BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0));
END decode4-16 ;
architecture behave of decode4-16 is
signal indata:std_logic_vector(2 downto 0);
begin
indata<=c&b&a;
process(indata)
begin
case indata is
when “0000”=>y<=”1111111111111110”;
when “0001”=>y<=”1111111111111101”;
when “0010”=>y<=”1111111111111011”;
when “0011”=>y<=”1111111111110111”;
when “0100”=>y<=”1111111111101111”;
when “0101”=>y<=”1111111111011111”;
when “0110”=>y<=”1111111110111111”;
when “0111”=>y<=”1111111101111111”;
when “1000”=>y<=”1111111011111111”;
when “1001”=>y<=”1111110111111111”;
when “1010”=>y<=”1111101111111111”;
when “1011”=>y<=”1111011111111111”;
when “1100”=>y<=”1110111111111111”;
when “1101”=>y<=”1101111111111111”;
when “1110”=>y<=”1011111111111111”;
when “1111”=>y<=”0111111111111111”;
when others=>y<=”xxxxxxxxxxxxxxxx”;
end case;
end process;
end behave;
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