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/* rtl81x9End.c - RealTek RTL81x9 Fast Ethernet interface header */ /* Copyright 1984-2000 Wind River Systems, Inc. */ /* modification history -------------------- 01f,17feb00,dgy Updated interrupt routine to ensure reserved interrupt bits are masked out prior to checking status. 01e,16feb00,dgy Updated rtl81x9HandleRecvInt to cover more checking within the loop that looks for RX biffer empty. 01d,16feb00,dgy Updated rtl81x9Wait to fix problem whereby always timed as checking incorrect register. 01c,28jan00,dgy Updated comments that refered to the wrong files. 01c,28jan00,dgy Updated comments that refered to the wrong files. 01b,28jan00,dgy Changed ryl81x9CsrReadByte to use the correct SYS_IN macro. 01a,29oct99,dgy created */ /* Theory of Operation I. Board Compatibility This device driver is designed for the RealTek RTL81x9, the RealTek Fast Ethernet controllers for PCI. This chip is used on a few clone boards. II. Board-specific settings PCI bus devices are configured by the system at boot time, so no jumpers need to be set on the board. The system BIOS will assign the PCI INTA signal to a (preferably otherwise unused) system IRQ line. III. Driver operation IIIa. Rx Ring buffers The receive unit uses a single linear ring buffer rather than the more common (and more efficient) descriptor-based architecture. Incoming frames are sequentially stored into the Rx region, and the host copies them into mBlks. IIIb. Tx operation The RTL81x9 uses a fixed set of four Tx descriptors in register space. EXTERNAL INTERFACE The only external interface is the rtl81x9EndLoad() routine, which expects the <initString> parameter as input. This parameter passes in a colon-delimited string of the format: <unit>:<devMemAddr>:<devIoAddr>:<pciMemBase:<vecNum>:<intLvl>:<memAdrs>: <memSize>:<memWidth>:<flags>:<buffMultiplier> The el3c90xEndLoad() function uses strtok() to parse the string. TARGET-SPECIFIC PARAMETERS .IP <unit> A convenient holdover from the former model. This parameter is used only in the string name for the driver. .IP <devMemAddr> This parameter in the memory base address of the device registers in the memory map of the CPU. It indicates to the driver where to find the register set. < This parameter should be equal to NONE if the device does not support memory mapped registers. .IP <devIoAddr> This parameter in the IO base address of the device registers in the IO map of some CPUs. It indicates to the driver where to find the RDP register. If both <devIoAddr> and <devMemAddr> are given then the device chooses <devMemAddr> which is a memory mapped register base address. This parameter should be equal to NONE if the device does not support IO mapped registers. . <pciMemBase> This parameter is the base address of the CPU memory as seen from the PCI bus. This parameter is zero for most intel architectures. .IP <vecNum> This parameter is the vector associated with the device interrupt. This driver configures the LANCE device to generate hardware interrupts for various events within the device; thus it contains an interrupt handler routine. The driver calls intConnect() to connect its interrupt handler to the interrupt vector generated as a result of the LANCE interrupt. .IP <intLvl> Some targets use additional interrupt controller devices to help organize and service the various interrupt sources. This driver avoids all board-specific knowledge of such devices. During the driver's initialization, the external routine sysRtl81x9IntEnable() is called to perform any board-specific operations required to allow the servicing of a NIC interrupt. For a description of sysRtl81x9IntEnable(), see "External Support Requirements" below. .IP <memAdrs> This parameter gives the driver the memory address to carve out its buffers and data structures. If this parameter is specified to be NONE then the driver allocates cache coherent memory for buffers and descriptors from the system pool. The 3C90x NIC is a DMA type of device and typically shares access to some region of memory with the CPU. This driver is designed for systems that directly share memory between the CPU and the NIC. It assumes that this shared memory is directly available to it without any arbitration or timing concerns. .IP <memSize> This parameter can be used to explicitly limit the amount of shared memory (bytes) this driver will use. The constant NONE can be used to indicate no specific size limitation. This parameter is used only if a specific memory region is provided to the driver. .IP <memWidth> Some target hardware that restricts the shared memory region to a specific location also restricts the access width to this region by the CPU. On these targets, performing an access of an invalid width will cause a bus error. This parameter can be used to specify the number of bytes of access width to be used by the driver during access to the shared memory. The constant NONE can be used to indicate no restrictions. Current internal support for this mechanism is not robust; implementation may not work on all targets requiring these restrictions. .IP <flags> This is parameter is used for future use, currently its value should be zero. EXTERNAL SUPPORT REQUIREMENTS This driver requires several external support functions, defined as macros: .CS SYS_INT_CONNECT(pDrvCtrl, routine, arg) SYS_INT_DISCONNECT (pDrvCtrl, routine, arg) SYS_INT_ENABLE(pDrvCtrl) SYS_INT_DISABLE(pDrvCtrl) SYS_OUT_BYTE(pDrvCtrl, reg, data) SYS_IN_BYTE(pDrvCtrl, reg, data) SYS_OUT_WORD(pDrvCtrl, reg, data) SYS_IN_WORD(pDrvCtrl, reg, data) SYS_OUT_LONG(pDrvCtrl, reg, data) SYS_IN_LONG(pDrvCtrl, reg, data) SYS_DELAY (delay) sysEl3c90xIntEnable(pDrvCtrl->intLevel) sysEl3c90xIntDisable(pDrvCtrl->intLevel) sysDelay (delay) .CE There are default values in the source code for these macros. They presume memory mapped accesses to the device registers and the normal intConnect(), and intEnable() BSP functions. The first argument to each is the device controller structure. Thus, each has access back to all the device-specific information. Having the pointer in the macro facilitates the addition of new features to this driver. The macros SYS_INT_CONNECT, SYS_INT_DISCONNECT, SYS_INT_ENABLE and SYS_INT_DISABLE allow the driver to be customized for BSPs that use special versions of these routines. The macro SYS_INT_CONNECT is used to connect the interrupt handler to the appropriate vector. By default it is the routine intConnect(). The macro SYS_INT_DISCONNECT is used to disconnect the interrupt handler prior to unloading the module. By default this is a dummy routine that returns OK. The macro SYS_INT_ENABLE is used to enable the interrupt level for the end device. It is called once during initialization. It calls an external board level routine sysRtl81x9IntEnable(). The macro SYS_INT_DISABLE is used to disable the interrupt level for the end device. It is called during stop. It calls an external board level routine sysRtl81x9IntDisable(). The macro SYS_DELAY is used for a delay loop. It calls an external board level routine sysDelay(delay). The granularity of delay is one microsecond. SYSTEM RESOURCE USAGE When implemented, this driver requires the following system resources: - one mutual exclusion semaphore - one interrupt vector - 24072 bytes in text for a I80486 target - 112 bytes in the initialized data section (data) - 0 bytes in the uninitialized data section (BSS) The driver allocates clusters of size 1536 bytes for receive frames and and transmit frames. There are 16 descriptors in the upload ring and 16 descriptors in the download ring. The buffer multiplier by default is 2, which me