PCIE接口的DMA存储方式硬件设计

XAPP859 (v1.1) July 31, 2008 www.xilinx.com 1

© Copyright 2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other

countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

Summary This application note provides a reference design for endpoint-initiated Direct Memory Access

(DMA) data transfers using the LogiCORE™ Endpoint Block Plus for Virtex

Virtex-5 FPGA integrated Endpoint block for PCI Express

®

designs and a single-rank, 64-bit,

256 MB DDR2 SDRAM memory. The reference design runs on the Virtex-5 FPGA ML555

development board for PCI Express designs. The reference design has these features:

the Endpoint on the Virtex-5 FPGA ML555 development board for PCI Express designs.

The host processor controls and monitors DMA transfers utilizing Programmed

bus.

interface (GUI) application running on the PC.

The Virtex-5 FPGA ML555 Development Kit for PCI Express

XAPP859 (v1.1) July 31, 2008 www.xilinx.com 2

Reference

System

1M bytes. In full duplex mode, read and write DMA transfer sizes can be different. The

hardware supports a DMA transfer size of 128 x m bytes (m = 1 through 8192), while the

GUI application software supports 128 x 2

times to repeat a given transfer.

XAPP859 (v1.1) July 31, 2008 www.xilinx.com 3

8K, 16K, 32K, or 64K bytes.

software), and negotiated link width (in lanes) of the DMA interface connection.

Demonstration mode runs through a complete sequence of read/write DMA transactions and

Upon completion of a DMA operation, the host PC processor firmware calculates the DMA

performance for the requested transaction and prints the result to the GUI log window. The

DMA performance does not include any overhead from the software setup of the host system

but does include DDR2 memory access latency for DMA writes. DMA performance for reads

includes the time to create memory read request packets, the turnaround time from Endpoint to

dma_ddr2_if.

allow evaluation of the core in a system-level simulation. ISE

For this design, the CORE Generator software is used to create the Virtex-5 FPGA Endpoint

Block Plus wrapper for PCI Express. The wrapper configures the integrated transceivers and

block, and connects block RAM elements for the transmit, receive, and retry buffers.

XAPP859 (v1.1) July 31, 2008 www.xilinx.com 4

XAPP859 (v1.1) July 31, 2008 www.xilinx.com 5