UG471 (v1.10) May 8, 2018 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
07/20/2012 1.2
(Cont’d)
Updated ILOGIC Resources. In Table 2-3, added T
ICOCKD
/T
IOCKDD
and removed
T
ICE1Q
. Updated Input Delay Resources (IDELAY). Updated functional description of
LD port in Table 2-4. In IDELAY Ports, updated Module Load - LD and
Increment/Decrement Signals - CE, INC, and added Pipeline Register Load -
LDPIPEEN and Pipeline Register Reset - REGRST. Removed Table 2-5: “Control Pin
Descriptions.” Updated descriptions of IDELAY_TYPE and IDELAY_VALUE in
Table 2-5. Updated IDELAY_TYPE Attribute, IDELAY_VALUE Attribute, and
HIGH_PERFORMANCE_MODE Attribute. Updated IDELAY Timing. Updated text
before Figure 2-12. Updated Stability after an Increment/Decrement Operation.
Updated IDELAYCTRL, including Figure 2-16. Added paragraph about OLOGICE2 and
OLOGICE3 to OLOGIC Resources. Updated first paragraph of Output Delay Resources
(ODELAY)—Not Available in HR Banks. Updated functions of REGRST, LD,
CNTVALUEIN, LDPIPEEN, and CNTVALUEOUT in Table 2-13. Added description of
VAR_LOAD_PIPE mode to Module Load - LD. Added Pipeline Register Load -
LDPIPEEN and Pipeline Register Reset - REGRST. Updated Count Value In -
CNTVALUEIN, Count Value Out - CNTVALUEOUT, and Increment/Decrement
Signals - CE, INC. Removed Table 2-14: “Control Pin Descriptions.” Updated
descriptions of ODELAY_TYPE and ODELAY_VALUE in Table 2-14. Updated ODELAY
Attributes. Added ODELAY Modes. Updated text before Figure 2-26.
Updated Reset Input - RST, page 149. Added INIT_Q and SRVAL_Q attributes to
Table 3-2. Updated bulleted list after Figure 3-6 and in MEMORY Interface Type.
Updated Figure 3-7. Updated ISERDESE2 Width Expansion, BITSLIP Submodule, and
Data Parallel-to-Serial Converter. Deleted the OCBEXTEND pin in Figure 3-14. Updated
descriptions of OFB and TFB in Table 3-6. Updated
Output Feedback from OSERDESE2
- OFB, 3-state Control Output - TFB, and Reset Input - RST, page 164. Updated
OSERDESE2 Clocking Methods and OSERDESE2 Width Expansion. Updated latencies
in Table 3-11. Added IO_FIFO Overview. Updated Resetting the IO_FIFO.
Added Appendix A, Termination Options for SSO Noise Analysis.
10/31/2012 1.3 Removed XC7V1500T from third bullet after Figure 1-7.
05/13/2014 1.4 Updated V
CCO
. Added item to bulleted list after Figure 1-7. Updated paragraph after
Figure 1-10. In VRN/VRP External Resistance Design Migration Guidelines, updated
first two paragraphs and added description of power rating. Updated title of Figure 1-11
and Figure 1-12. Updated step 4 of DCI in 7 Series FPGAs I/O Standards. Updated
Figure 1-14. Updated first paragraph of Uncalibrated Split Termination in High-Range
I/O Banks (IN_TERM). Added IOBUF_DCIEN, IOBUF_INTERMDISABLE,
IOBUFDS_DIFF_OUT_DCIEN, IOBUFDS_DIFF_OUT_INTERMDISABLE, and
IOBUFDS_INTERMDISABLE to 7 Series FPGA SelectIO Primitives. Removed O output
from Figure 1-22 and following description. Updated HSTL_ II_T_DCI and HSTL_
II_T_DCI_18. Added IBUFDS_DIFF_OUT_INTERMDISABLE, IOBUF_DCIEN, and
IOBUF_INTERMDISABLE. Updated connections in Figure 1-28, Figure 1-30,
Figure 1-31, and Figure 1-32. Reversed R
VRN
and R
VRP
in Figure 1-46, Figure 1-48,
Figure 1-49, Figure 1-50, Figure 1-52, Figure 1-54, Figure 1-55, Figure 1-56, Figure 1-57,
Figure 1-58, Figure 1-60, Figure 1-62, and Figure 1-63. Added note to SSTL18_II, SSTL15,
SSTL135, DIFF_SSTL18_II, DIFF_SSTL15, DIFF_SSTL135. Updated fifth paragraph of
SSTL (Stub-Series Terminated Logic). Removed Thevenin equivalent of R/2 and
description of source termination series resistors from SSTL18_I_DCI,
DIFF_SSTL18_I_DCI, SSTL18_II, SSTL15, SSTL135, DIFF_SSTL18_II, DIFF_SSTL15,
DIFF_SSTL135, SSTL18_II_DCI, SSTL_15_DCI, SSTL135_DCI, DIFF_SSTL18_II_DCI,
DIFF_SSTL_15_DCI, DIFF_ SSTL135_DCI, SSTL18_II_T_DCI, SSTL15_T_DCI,
SSTL135_T_DCI, DIFF_SSTL18_II_T_DCI, DIFF_SSTL15_T_DCI, DIFF_
SSTL135_T_DCI, and SSTL12, SSTL12_DCI, SSTL12_T_DCI, DIFF_SSTL12,
DIFF_SSTL12_DCI, DIFF_SSTL12_T_DCI. Updated Figure 1-57 and Figure 1-59.
Date Version Revision
