S32K144referencemanual_s32k144中文参考手册,s32k144芯片中文手册资源-CSDN文库

4星 · 超过85%的资源需积分: 50 78 浏览量 2017-02-27 09:39:36 上传评论 2 收藏 15.73MB PDF 举报

根据提供的文档信息，我们可以提取并总结出关于S32K144参考手册的重要知识点。 ### S32K144 参考手册 #### 一、关于本手册本手册旨在为用户提供有关S32K144微控制器的详细信息。其目标读者包括系统设计工程师、应用开发人员以及任何需要了解S32K144特性和功能的专业人士。手册组织结构清晰，分为多个章节，每个章节涵盖了不同方面的内容。 - **组织结构**：手册分为多个章节，每一章都有明确的主题，便于用户快速查找所需信息。 - **模块描述**：手册对S32K144的各个模块进行了详细介绍，包括但不限于芯片特定的信息、与其他章节相关的交叉引用等。 - **寄存器描述**：提供关于各种寄存器的功能、地址、位字段等详细信息，帮助开发者更好地控制硬件资源。 - **约定**：介绍了手册中使用的术语、警告标识、数字系统等方面的约定，以确保用户能够准确理解文档内容。 #### 二、介绍 ##### 2.1 概览 - **设备简介**：S32K144是一款高性能、低功耗的微控制器，基于ARM Cortex-M4F内核。 - **特性概览**：提供了S32K144的主要技术规格，如内存容量、外设接口、时钟频率等。 - **功能分类**：将S32K144的功能模块分为几个大类，便于理解其架构组成。 - **块图**：通过图形化的形式展示了S32K144内部主要组件之间的连接关系。 - **特性比较**：与同类产品进行比较，突出S32K144的优势之处。 ##### 2.2 功能模块 - **ARM Cortex-M4F 内核模块**：详细介绍了核心处理器的配置，包括总线系统、中断控制器、调试设施等。 - **系统模块**：涵盖电源管理、复位、时钟管理等功能。 - **存储器与存储器接口**：包括各种类型的存储器（如RAM、Flash）及其接口。 - **时钟**：介绍时钟源、时钟分频器等相关组件。 - **安全与完整性模块**：提供数据加密、安全启动等安全特性。 - **模拟模块**：如ADC、DAC等模拟信号处理单元。 - **定时器模块**：包含多种定时器，用于精确的时间测量。 - **通信接口**：支持多种通信协议（如SPI、I2C、UART等）。 - **人机交互接口**：如按键、LED等外部设备的接口。 #### 三、核心概述 ##### 3.1 ARM Cortex-M4F 内核配置 - **总线、互连与接口**：详细说明了Cortex-M4F内核中各种总线的用途及互连机制。 - **系统滴答定时器**：用于实现周期性中断的功能。 - **调试设施**：提供了一系列工具和支持，方便开发者进行代码调试。 - **缓存**：介绍数据缓存和指令缓存的工作原理。 - **核心特权级别**：解释了内核在不同级别的权限设置，确保系统的安全性。 ##### 3.2 Nested Vectored Interrupt Controller (NVIC) 配置 - **中断优先级级别**：定义了不同中断的优先级设置。 - **不可屏蔽中断**：介绍了不可屏蔽中断的特点及应用场景。 - **中断配置位置**：指导用户如何确定配置特定中断所需的位字段和寄存器位置。 ##### 3.3 Asynchronous Wake-up Interrupt Controller (AWIC) 配置 - **唤醒源**：说明了可以引起系统从低功耗状态唤醒的各种触发源。 ##### 3.4 FPU 配置 - **浮点单元**：描述了S32K144中的浮点运算单元，提高了数学计算性能。 ##### 3.5 JTAG 控制器配置 - **JTAG 控制器**：用于实现硬件级别的调试功能。 #### 四、存储器管理接下来的部分会详细介绍S32K144的存储器管理，包括各种类型的存储器（如RAM、Flash）、存储器接口等内容，这部分内容在文档中尚未完全给出，但可以推测会包括： - **存储器类型**：详细描述了S32K144支持的不同类型的存储器及其特性。 - **存储器接口**：介绍了连接外部存储器的方法。 - **存储器映射**：提供了S32K144内部存储器和外设的地址空间布局。 - **存储器保护单元**：解释了存储器保护单元的工作原理及其在提高系统安全性方面的作用。以上内容基于S32K144参考手册的部分章节信息进行了详细解读。对于深入理解和使用S32K144微控制器来说，这份手册是非常宝贵的资源。

资源推荐

资源详情

资源评论

For Assessment Purposes Only

S32K144 Reference Manual

Document Number: S32K144RM

Rev. 1 Draft H, 02/2016

Review Draft

Freescale Confidential Proprietary - Non-Disclosure Agreement required

For Assessment Purposes Only

Contents

Section number Title Page

Chapter 1

About This Manual

1.1 Audience....................................................................................................................................................................... 41

1.2 Organization..................................................................................................................................................................41

1.3 Module descriptions......................................................................................................................................................41

1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 42

1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 43

1.4 Register descriptions.....................................................................................................................................................44

1.5 Conventions.................................................................................................................................................................. 45

1.5.1 Notes, Cautions, and Warnings......................................................................................................................45

1.5.2 Numbering systems........................................................................................................................................45

1.5.3 Typographic notation..................................................................................................................................... 46

1.5.4 Special terms..................................................................................................................................................46

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................49

2.2 Device Introduction...................................................................................................................................................... 49

2.3 Feature Summary..........................................................................................................................................................50

2.4 Block Diagram..............................................................................................................................................................53

2.5 Feature comparison.......................................................................................................................................................54

2.6 Module Functional Categories......................................................................................................................................56

2.6.1 ARM Cortex-M4F Core Modules..................................................................................................................57

2.6.2 System Modules.............................................................................................................................................57

2.6.3 Memories and Memory Interfaces................................................................................................................. 58

2.6.4 Clocks.............................................................................................................................................................59

2.6.5 Security and Integrity modules...................................................................................................................... 59

2.6.6 Analog modules............................................................................................................................................. 59

2.6.7 Timer modules............................................................................................................................................... 60

S32K144 Reference Manual, Rev. 1 Draft H, 02/2016

Freescale Semiconductor, Inc.

Review Draft

Freescale Confidential Proprietary - Non-Disclosure Agreement required

For Assessment Purposes Only

Section number Title Page

2.6.8 Communication interfaces............................................................................................................................. 60

2.6.9 Human-machine interfaces............................................................................................................................ 61

Chapter 3

Core Overview

3.1 ARM Cortex-M4F Core Configuration........................................................................................................................ 63

3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 64

3.1.2 System Tick Timer.........................................................................................................................................64

3.1.3 Debug facilities.............................................................................................................................................. 64

3.1.4 Caches............................................................................................................................................................ 64

3.1.5 Core privilege levels...................................................................................................................................... 65

3.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 66

3.2.1 Interrupt priority levels.................................................................................................................................. 66

3.2.2 Non-maskable interrupt..................................................................................................................................66

3.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 67

3.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................68

3.3.1 Wake-up sources............................................................................................................................................68

3.4 FPU Configuration........................................................................................................................................................69

3.5 JTAG Controller Configuration....................................................................................................................................69

Chapter 4

Memories and Memory Interfaces

4.1 Flash Memory Configuration........................................................................................................................................71

4.1.1 Flash memory types....................................................................................................................................... 71

4.1.2 Flash Memory Sizes.......................................................................................................................................72

4.1.3 Flash Memory Map........................................................................................................................................72

4.1.4 Flash Security.................................................................................................................................................72

4.1.5 Flash Program Restrictions............................................................................................................................ 73

4.1.6 Flash Modes................................................................................................................................................... 73

4.1.7 Erase All Flash Contents................................................................................................................................73

4.1.8 FTFE_FOPT Register.................................................................................................................................... 73

S32K144 Reference Manual, Rev. 1 Draft H, 02/2016

Review Draft

Freescale Semiconductor, Inc.

Freescale Confidential Proprietary - Non-Disclosure Agreement required

For Assessment Purposes Only

Section number Title Page

4.2 Flash Memory Controller Configuration...................................................................................................................... 73

4.2.1 Number of masters.........................................................................................................................................74

4.3 SRAM Configuration....................................................................................................................................................74

4.3.1 SRAM sizes....................................................................................................................................................75

4.3.2 SRAM retention in low power modes............................................................................................................76

4.3.3 SRAM accesses..............................................................................................................................................76

4.3.4 SRAM arbitration and priority control...........................................................................................................77

Chapter 5

Memory Map

5.1 Introduction...................................................................................................................................................................79

5.2 Aliased bit-band regions............................................................................................................................................... 79

5.3 Flash Memory Map.......................................................................................................................................................80

5.3.1 Alternate Non-Volatile IRC User Trim Description......................................................................................81

5.4 SRAM memory map.....................................................................................................................................................81

5.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................82

5.5.1 Read-after-write sequence and required serialization of memory operations................................................82

5.6 Private Peripheral Bus (PPB) memory map..................................................................................................................83

Chapter 6

Clock Distribution

6.1 Introduction...................................................................................................................................................................85

6.2 High level clocking diagram.........................................................................................................................................85

6.3 Clock definitions...........................................................................................................................................................86

6.4 Internal clocking requirements..................................................................................................................................... 88

6.4.1 Clock divider values after reset......................................................................................................................90

6.4.2 HSRUN mode clocking................................................................................................................................. 91

6.4.3 VLPR mode clocking.....................................................................................................................................91

6.5 Clock Gating.................................................................................................................................................................91

6.6 Module clocks...............................................................................................................................................................92

6.6.1 PCC connections............................................................................................................................................93

S32K144 Reference Manual, Rev. 1 Draft H, 02/2016

Freescale Semiconductor, Inc.

Review Draft

Freescale Confidential Proprietary - Non-Disclosure Agreement required