RTL8309M-CG
SINGLE-CHIP 9-PORT 10/100M ETHERNET
SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.1
07 January 2014
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8309M
Datasheet
Single-Chip 9-Port 10/100Mbps Ethernet Switch Controller
ii Track ID: JATR-8275-15 Rev. 1.1
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TRADEMARKS
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USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary
1.0 2013/06/22 First release.
1.1 2014/01/07 Revised Table 3, page 9 (pin 51 description)
Revised Table 6, page 11 (pin 34, 33, and 52 descriptions)
RTL8309M
Datasheet
Single-Chip 9-Port 10/100Mbps Ethernet Switch Controller
iii Track ID: JATR-8275-15 Rev. 1.1
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
2. FEATURES.........................................................................................................................................................................2
3. SYSTEM APPLICATIONS...............................................................................................................................................3
4. BLOCK DIAGRAM...........................................................................................................................................................4
5. PIN ASSIGNMENTS .........................................................................................................................................................5
5.1. PIN ASSIGNMENTS DIAGRAM .......................................................................................................................................5
5.2. PACKAGE IDENTIFICATION...........................................................................................................................................5
5.3. PIN ASSIGNMENTS TABLE ............................................................................................................................................6
6. PIN DESCRIPTIONS.........................................................................................................................................................8
6.1. PIN ASSIGNMENT CODES .............................................................................................................................................8
6.2. MEDIA CONNECTION PINS ...........................................................................................................................................8
6.3. (T)MII/RMII PORT MAC INTERFACE PINS..................................................................................................................9
6.4. MISCELLANEOUS PINS ...............................................................................................................................................10
6.5. PORT LED PINS .........................................................................................................................................................11
6.6. STRAPPING PINS.........................................................................................................................................................11
6.7. LDO PINS ..................................................................................................................................................................13
6.8. POWER AND GND PINS ..............................................................................................................................................13
7. BASIC FUNCTIONAL DESCRIPTION........................................................................................................................14
7.1. SWITCH CORE FUNCTION OVERVIEW.........................................................................................................................14
7.1.1. Flow Control ........................................................................................................................................................14
7.1.1.1 IEEE 802.3x Full Duplex Flow Control........................................................................................................................14
7.1.1.2 Half Duplex Back Pressure...........................................................................................................................................14
7.1.2. Address Search, Learning, and Aging..................................................................................................................15
7.1.3. Half Duplex Operation.........................................................................................................................................15
7.1.4. InterFrame Gap....................................................................................................................................................15
7.1.5. Illegal Frame........................................................................................................................................................15
7.2. PHYSICAL LAYER FUNCTIONAL OVERVIEW ...............................................................................................................16
7.2.1. Auto-Negotiation ..................................................................................................................................................16
7.2.2. 10Base-T Transmit Function................................................................................................................................16
7.2.3. 10Base-T Receive Function..................................................................................................................................16
7.2.4. Link Monitor.........................................................................................................................................................16
7.2.5. 100Base-TX Transmit Function............................................................................................................................16
7.2.6. 100Base-TX Receive Function..............................................................................................................................16
7.2.7. Power-Down Mode...............................................................................................................................................17
7.2.8. Crossover Detection and Auto Correction ...........................................................................................................17
7.2.9. Polarity Detection and Correction.......................................................................................................................17
7.3. GENERAL FUNCTION OVERVIEW................................................................................................................................18
7.3.1. Power-On Sequence .............................................................................................................................................18
7.3.2. Setup and Configuration.......................................................................................................................................19
7.3.3. Serial EEPROM Example.....................................................................................................................................20
7.3.3.1 EEPROM Device Operation .........................................................................................................................................20
7.3.3.2 EEPROM Size Selection...............................................................................................................................................22
7.3.4. SMI .......................................................................................................................................................................22
7.3.5. (T)MII/RMII Port (The 9th Port)..........................................................................................................................23
7.3.5.1 PHY Mode (T)MII........................................................................................................................................................23
7.3.5.2 MAC Mode (T)MII.......................................................................................................................................................23
7.3.5.3 RMII .............................................................................................................................................................................24
7.3.6. Head-Of-Line Blocking ........................................................................................................................................24
RTL8309M
Datasheet
Single-Chip 9-Port 10/100Mbps Ethernet Switch Controller
iv Track ID: JATR-8275-15 Rev. 1.1
7.3.7. Filtering/Forwarding Reserved Control Frame...................................................................................................25
7.3.8. Loop Detection .....................................................................................................................................................25
7.3.9. Reg.0.14 PHY Digital Loopback Return to Internal.............................................................................................27
7.3.10. LDO for 1.0V Power Generation.....................................................................................................................28
7.3.11. Crystal/Oscillator............................................................................................................................................28
8. ADVANCED FUNCTION DESCRIPTION...................................................................................................................29
8.1. VLAN FUNCTION ......................................................................................................................................................29
8.1.1. VLAN Description ................................................................................................................................................29
8.1.2. Port-Based VLAN.................................................................................................................................................30
8.1.3. IEEE 802.1Q Tagged-VID Based VLAN..............................................................................................................30
8.1.4. Insert/Remove/Replace Tag..................................................................................................................................30
8.1.5. Ingress and Egress Rules......................................................................................................................................31
8.2. IEEE 802.1P REMARKING FUNCTION.........................................................................................................................31
8.3. QOS FUNCTION ..........................................................................................................................................................32
8.3.1. Bandwidth Control ...............................................................................................................................................32
8.3.1.1 Output (TX) Bandwidth Control...................................................................................................................................32
8.3.1.2 Input (RX) Bandwidth Control .....................................................................................................................................33
8.3.2. Priority Assignment..............................................................................................................................................33
8.3.2.1 Queue Number Selection ..............................................................................................................................................33
8.3.2.2 Port-Based Priority Assignment....................................................................................................................................33
8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment..................................................................................................................34
8.3.2.4 DSCP-Based Priority Assignment ................................................................................................................................34
8.3.2.5 IP Address-Based Priority.............................................................................................................................................34
8.3.2.6 Reassigned Priority .......................................................................................................................................................34
8.3.2.7 RLDP-Based Priority....................................................................................................................................................34
8.3.2.8 Packet Priority Selection...............................................................................................................................................35
8.4. LOOKUP TABLE FUNCTION ........................................................................................................................................36
8.4.1. Function Description............................................................................................................................................36
8.4.2. Address Search, Learning, and Aging..................................................................................................................36
8.4.3. Lookup Table Definition.......................................................................................................................................38
8.5. STORM FILTER FUNCTION ..........................................................................................................................................38
8.6. INPUT AND OUTPUT DROP FUNCTION ........................................................................................................................39
8.7. LED FUNCTION..........................................................................................................................................................40
8.8. ENERGY-EFFICIENT ETHERNET (EEE) .......................................................................................................................41
8.9. CABLE DIAGNOSIS .....................................................................................................................................................41
9. CHARACTERISTICS......................................................................................................................................................42
9.1. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS ...............................................................................................42
9.2. OPERATING RANGE....................................................................................................................................................42
9.3. DC CHARACTERISTICS...............................................................................................................................................42
9.4. DIGITAL TIMING CHARACTERISTICS ..........................................................................................................................43
9.4.1. (T)MII/RMII Interface Timing..............................................................................................................................43
9.4.1.1 MII MAC Mode Timing ...............................................................................................................................................43
9.4.1.2 MII PHY Mode Timing ................................................................................................................................................44
9.4.1.3 TMII MAC Mode Timing.............................................................................................................................................44
9.4.1.4 TMII PHY Mode Timing..............................................................................................................................................45
9.4.1.5 RMII Timing.................................................................................................................................................................45
9.4.2. LED Timing..........................................................................................................................................................45
9.4.3. Reception/Transmission Data Timing of SMI Interface .......................................................................................46
9.4.4. EEPROM Auto-Load Timing................................................................................................................................47
10. MECHANICAL DIMENSIONS.................................................................................................................................48
10.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................49
11. ORDERING INFORMATION...................................................................................................................................49
RTL8309M
Datasheet
Single-Chip 9-Port 10/100Mbps Ethernet Switch Controller
v Track ID: JATR-8275-15 Rev. 1.1
List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE ..............................................................................................................................................6
TABLE 2. MEDIA CONNECTION PINS..............................................................................................................................................8
TABLE 3. MII PORT MAC INTERFACE PINS...................................................................................................................................9
TABLE 4. MISCELLANEOUS PINS .................................................................................................................................................10
TABLE 5. PORT LED PINS............................................................................................................................................................11
TABLE 6. STRAPPING PINS ...........................................................................................................................................................11
TABLE 7. LDO PINS.....................................................................................................................................................................13
TABLE 8. POWER AND GND PINS ................................................................................................................................................13
TABLE 9. BASIC SMI READ/WRITE CYCLES................................................................................................................................22
TABLE 10. EXTENDED SMI MANAGEMENT FRAME FORMAT ........................................................................................................22
TABLE 11. RESERVED ETHERNET MULTICAST ADDRESSES...........................................................................................................25
TABLE 12. LOOP FRAME FORMAT .................................................................................................................................................26
TABLE 13. CRYSTAL AND OSCILLATOR REQUIREMENTS...............................................................................................................28
TABLE 14. VLAN TABLE..............................................................................................................................................................29
TABLE 15. VLAN ENTRY .............................................................................................................................................................29
TABLE 16. L2 TABLE 4-WAY HASH INDEX METHOD ....................................................................................................................37
TABLE 17. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS .................................................................................................42
TABLE 18. OPERATING RANGE......................................................................................................................................................42
TABLE 19. DC CHARACTERISTICS.................................................................................................................................................42
TABLE 20. MII MAC MODE TIMING.............................................................................................................................................43
TABLE 21. MII PHY MODE TIMING..............................................................................................................................................44
TABLE 22. TMII MAC MODE TIMING ..........................................................................................................................................44
TABLE 23. TMII PHY MODE TIMING ...........................................................................................................................................45
TABLE 24. RMII TIMING...............................................................................................................................................................45
TABLE 25. LED TIMING ................................................................................................................................................................45
TABLE 26. SMI TIMING.................................................................................................................................................................46
TABLE 27. EEPROM AUTO-LOAD TIMING CHARACTERISTICS ....................................................................................................47
TABLE 28. ORDERING INFORMATION ............................................................................................................................................49
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