2017.08.22 (REV 0.0) NVP6158C Data sheet
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TABLE OF CONTENTS
Revision History ......................................................................................................................................................... 2
Contents of Tables ...................................................................................................................................................... 7
Contents of Figures .................................................................................................................................................... 8
Chapter 1 PIN INFORMATION ................................................................................................................................ 9
1.1 PIN ASSIGNMENTS ................................................................................................................................... 9
1.2 PIN DESCRIPTION .................................................................................................................................. 10
Chapter 2 UNIVERSAL RX(1M to 8M7.5P) .......................................................................................................... 12
2.1 FUNCTIONAL OVERVIEW ...................................................................................................................... 12
2.1 ANALOG FRONT END (CLAMP, ANTI-ALIASING FILTER, EQ FILTER) ................................................ 13
2.2 GENLOCK (ROBUST SYNC DETECTION, ROBUST NO-VIDEO DETECTION) ................................... 13
2.3 YCS (Y/C SEPARATOR) .......................................................................................................................... 13
2.4 LUMA PROCESSING ............................................................................................................................... 13
2.5 CHROMA PROCESSING ......................................................................................................................... 13
2.6 DATA OUTPUT ORDER & DIRECTION CONTROL ................................................................................ 14
2.7 OUTPUT FORMAT ................................................................................................................................... 15
2.7.1 ITU-R BT.656/BT.1120 FORMAT ................................................................................................... 15
2.7.2 ITU-R BT.601 FORMAT ................................................................................................................. 15
2.7.3 VIDEO OUTPUT TIMING INFORMATION .................................................................................... 16
2.8 OUTPUT MODE ....................................................................................................................................... 18
2.8.1 SINGLE OUTPUT MODE .............................................................................................................. 18
2.8.2 2-MULTIPLEX OUTPUT MODE .................................................................................................... 19
2.8.3 4-MULTIPLEX OUTPUT MODE .................................................................................................... 20
2.9 297MHz INTERFACE AND MULTI STANDARD OUTPUT MODE ........................................................... 22
2.10 Video Frame Control ................................................................................................................................. 22
2.11 MOTION DETECTOR ............................................................................................................................... 23
Chapter 3 AUDIO CODEC ..................................................................................................................................... 24
3.1 Record Output .......................................................................................................................................... 24
3.1.1 Data Output Interface .................................................................................................................... 25
3.1.2 2/4/8/16-Channel Data Output(256 fs) .......................................................................................... 26
3.1.3 2/4/8/16-Channel Audio Data Output with 2-Channel Mic Data(320 fs) ........................................ 27
3.1.4 ADATA_SP Output ......................................................................................................................... 28
3.2 Playback Output ....................................................................................................................................... 29
3.3 Audio Detection ........................................................................................................................................ 29
3.4 Cascade Operation ................................................................................................................................... 29
Chapter 4 COAXIAL PROTOCOL ......................................................................................................................... 30
4.1 PELCO PROTOCOL ................................................................................................................................ 30
4.2 A-CP(AHD-Coaxial protocol) .................................................................................................................... 31
Chapter 5 I2C INTERFACE ................................................................................................................................... 33
Chapter 6 REGISTER DESCRIPTION .................................................................................................................. 34
6.1 REGISTER ADDRESS ............................................................................................................................. 34
6.1.1 BANK0 Register(0x00~0x1F) : VIDEO .......................................................................................... 34
6.1.2 BANK0 Register(0x20~0x3F) : VIDEO .......................................................................................... 35
6.1.3 BANK0 Register(0x40~0x5F) : VIDEO .......................................................................................... 36
6.1.4 BANK0 Register(0x60~0x7F) : VIDEO .......................................................................................... 37
6.1.5 BANK0 Register(0x80~0xA3) : VIDEO_ENABLE & Delay ............................................................ 38
6.1.6 BANK0 Register(0xA8~0xF5) : STATUS ....................................................................................... 39
6.1.7 BANK1 Register(0x00~0x1F) : AUDIO .......................................................................................... 40
6.1.8 BANK1 Register(0x20~0x44) : AUDIO .......................................................................................... 41
6.1.9 BANK1 Register(0x80~0x9F) : IP Power Down ............................................................................ 42
6.1.10 BANK1 Register(0xB0~0xBF) : MPP ............................................................................................. 42
6.1.11 BANK1 Register(0xC0~0xCF) : OUTPUT PORT .......................................................................... 42
6.1.12 BANK2 Register(0x00~0x1F) : MOTION ....................................................................................... 43
6.1.13 BANK3~4 Register(0x00~0x7F / 0x80~0xFF ) : COAXIAL ........................................................... 44
6.1.14 BANK3~4 Register(0x00~0x1F / 0x80~0x9F ) : COAXIAL CH1~4 ............................................... 45
6.1.15 BANK3~4 Register(0x20~0x5F / 0xA0~0xDF ) : COAXIAL CH1~4 .............................................. 46
6.1.16 BANK3~4 Register(0x60~0x79 / 0xE0~0xF9 ) : COAXIAL CH1~4 ............................................... 47
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