NVM Express 1.1
3
Table of Contents
1 INTRODUCTION ............................................................................................................. 8
1.1 Overview ......................................................................................................................................... 8
1.2 Scope .............................................................................................................................................. 8
1.3 Outside of Scope ............................................................................................................................ 8
1.4 Theory of Operation ........................................................................................................................ 8
1.4.1 Multi-Path I/O and Namespace Sharing ............................................................................................... 10
1.5 Conventions .................................................................................................................................. 13
1.6 Definitions ..................................................................................................................................... 14
1.6.1 Admin Queue ....................................................................................................................................... 14
1.6.2 arbitration burst .................................................................................................................................... 14
1.6.3 arbitration mechanism .......................................................................................................................... 14
1.6.4 candidate command ............................................................................................................................. 14
1.6.5 command completion ........................................................................................................................... 14
1.6.6 command submission ........................................................................................................................... 14
1.6.7 controller .............................................................................................................................................. 14
1.6.8 extended LBA ....................................................................................................................................... 14
1.6.9 firmware slot ......................................................................................................................................... 14
1.6.10 I/O command ........................................................................................................................................ 14
1.6.11 I/O Completion Queue .......................................................................................................................... 14
1.6.12 I/O Submission Queue ......................................................................................................................... 14
1.6.13 LBA range ............................................................................................................................................ 15
1.6.14 logical block .......................................................................................................................................... 15
1.6.15 logical block address (LBA) .................................................................................................................. 15
1.6.16 metadata .............................................................................................................................................. 15
1.6.17 namespace ........................................................................................................................................... 15
1.6.18 Namespace ID...................................................................................................................................... 15
1.6.19 NVM ..................................................................................................................................................... 15
1.6.20 NVM subsystem ................................................................................................................................... 15
1.6.21 private namespace ............................................................................................................................... 15
1.6.22 shared namespace ............................................................................................................................... 15
1.7 Keywords ...................................................................................................................................... 15
1.7.1 mandatory ............................................................................................................................................ 15
1.7.2 may ...................................................................................................................................................... 15
1.7.3 optional ................................................................................................................................................. 16
1.7.4 R ........................................................................................................................................................... 16
1.7.5 reserved ............................................................................................................................................... 16
1.7.6 shall ...................................................................................................................................................... 16
1.7.7 should ................................................................................................................................................... 16
1.8 Conventions .................................................................................................................................. 16
1.9 Byte, word and Dword Relationships ............................................................................................ 17
1.10 References ................................................................................................................................ 17
1.11 References Under Development ............................................................................................... 18
2 SYSTEM BUS (PCI EXPRESS) REGISTERS ....................................................................... 19
2.1 PCI Header ................................................................................................................................... 19
2.1.1 Offset 00h: ID - Identifiers .................................................................................................................... 20
2.1.2 Offset 04h: CMD - Command ............................................................................................................... 20
2.1.3 Offset 06h: STS - Device Status........................................................................................................... 20
2.1.4 Offset 08h: RID - Revision ID ............................................................................................................... 20
2.1.5 Offset 09h: CC - Class Code ................................................................................................................ 21
2.1.6 Offset 0Ch: CLS – Cache Line Size ..................................................................................................... 21
2.1.7 Offset 0Dh: MLT – Master Latency Timer ............................................................................................ 21
2.1.8 Offset 0Eh: HTYPE – Header Type ...................................................................................................... 21
2.1.9 Offset 0Fh: BIST – Built In Self Test (Optional) .................................................................................... 21
2.1.10 Offset 10h: MLBAR (BAR0) – Memory Register Base Address, lower 32-bits ..................................... 21
2.1.11 Offset 14h: MUBAR (BAR1) – Memory Register Base Address, upper 32-bits .................................... 22
2.1.12 Offset 18h: IDBAR (BAR2) – Index/Data Pair Register Base Address (Optional) ................................ 22