26. How do I simulate with multiple SDF files? ................................................................................15
27. ModelSim runs the simulation for the worst case temperature value. How can we simulate our
design for both the best case and the worst case temperature values on ModelSim?..........................16
28. Is it possible to simulate the JTAG interface within ModelSim?.................................................16
Post-Synthesis vs. Pre-Synthesis Simulation (Mismatch/Errors)........................... 17
29. My post-synthesis simulation is different than my pre-synthesis simulation. Why?...................17
30. Pre synthesis simulation runs but post synthesis simulation displays all outputs in red. Why? 17
31. **Error: (vsim-3170) Count not find ''<Project_Dir>\simulation\presynth.testbench' Error
loading design ........................................................................................................................................17
32. #error: (vsim-23)unable to change to directory path "postsynth.test" #No such file or
directory.(errno=ENOENT).....................................................................................................................17
Post-Layout Simulation Errors...................................................................................19
33. Why does the simulation show no violation of setup and hold times, but the simulator returns a
warning? .................................................................................................................................................19
34. Why there is a difference between the results of the static timing analysis in Designer and
post-layout simulation with ModelSim? ..................................................................................................19
35. Timing Violation errors or warnings during post layout simulation.............................................19
Known Issues ..............................................................................................................20
36. When I run ModelSim, my computer hangs, with "vsimk.exe" at 100% CPU usage. I cannot
shut down ModelSim during this time. I must wait about 10 minutes until vsmik.exe stops running.
Why? 20
37. In PLL simulation (pre-synth, post-synth and post route) some output frequencies do not show
up as expected. ......................................................................................................................................20
38. Post-synthesis and post-layout simulation gives invalid results for the INOUT bus. INOUT bus
with initial value 'U' Within Netlist Causes Unknown In Post-Synthesis and Post-Layout Simulation.
How do I get a valid result? ....................................................................................................................21
39. SmartPower does not annotate all pins when the VCD file generated by ModelSim is imported
into Designer. .........................................................................................................................................21
Miscellaneous..............................................................................................................22
40. ModelSim Simulation Error #**Fatal:(vsim-3881).......................................................................22
41. How do I simulate two Actel FPGAs together in a system simulation?......................................22
42. Failed to find instance # ERROR: C:/Designs/annotations/interface.sdf(15): Failed to find
INSTANCE '/testbench/ramwrn_1' # ERROR: C:/Designs/annotations/interface.sdf(24): Failed to find
INSTANCE '/testbench/block_1'.............................................................................................................22
43. # Error: couldn't open socket: invalid argument Trouble making server....................................23
44. ** Error: (vsim-3174) Package 'D:\Actel\Libero_v8.4\Model\std.standard' requires a body.......23
45. I cannot get the input waveforms that I defined in Waveformer Lite to match the input
waveforms that are shown in ModelSim when I run simulation. Why? ..................................................23
46. Why are the backannotated timing results different than what I can see in SmartTime?..........23
47. In Libero IDE Project Manager Settings there is a way to send extra command line arguments
to the VSIM command. Is there a way to add a command line argument to the vlog command?.........24
Useful Links.................................................................................................................25
