C8051F320芯片资料

Full Speed USB, 16k ISP FLASH MCU Family

C8051F320/1

Preliminary Rev. 1.1 12/03 Copyright © 2003 by Silicon Laboratories C8051F320/1-DS11

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

ANALOG PERIPHERALS

- 10-Bit ADC

• Up to 200 ksps

• Up to 17 or 13 External Single-Ended or Differential

- USB Specification 2.0 Compliant

- Full Speed (12 Mbps) or Low Speed (1.5 Mbps)

Operation

- Integrated Clock Recovery; No External Crystal

Required for Full Speed or Low Speed

- Supports Eight Flexible Endpoints

- 1k Byte USB Buffer Memory

- Integrated Transceiver; No External Resistors Required

ICE-Chips, Target Pods, and Sockets

VOLTAGE REGULATOR INPUT: 4.0V TO 5.25V

HIGH SPEED 8051 µC Core

- Pipelined Instruction Architecture; Executes 70% of

Instructions in 1 or 2

- Up to 25 MIPS Throughput with 25 MHz Clock

- Expanded Interrupt Handler

MEMORY

- 2304 Bytes Internal RAM (1k + 256 + 1k USB FIFO)

- 16k Bytes FLASH; In-system programmable in 512-byte

Sectors

- Hardware Enhanced SPI™, Enhanced UART, and

- Internal Oscillator: 0.25% Accuracy with Clock

- External Oscillator: Crystal, RC, C, or Clock (1 or 2 Pin

Modes)

- Can Switch Between Clock Sources on-the-fly; Useful in

- 32-pin LQFP (C8051F320)

- 28-pin MLP (C8051F321)

C8051F320/1

C8051F320/1

1. SYSTEM OVERVIEW .........................................................................................................17

1.1. CIP-51™ Microcontroller Core ......................................................................................20

1.1.1. Fully 8051 Compatible ..........................................................................................20

1.1.2. Improved Throughput ............................................................................................20

1.1.3. Additional Features................................................................................................21

1.2. On-Chip Memory ............................................................................................................22

1.3. Universal Serial Bus Controller.......................................................................................23

1.4. Voltage Regulator............................................................................................................23

5.1. Analog Multiplexer .........................................................................................................40

5.2. Temperature Sensor.........................................................................................................41

5.3. Modes of Operation.........................................................................................................42

5.3.1. Starting a Conversion.............................................................................................42

5.3.2. Tracking Modes .....................................................................................................43

5.3.3. Settling Time Requirements ..................................................................................44

5.4. Programmable Window Detector ....................................................................................50

5.4.1. Window Detector In Single-Ended Mode .............................................................52

6. VOLTAGE REFERENCE....................................................................................................55

9.1.1. Instruction and CPU Timing..................................................................................75

9.2. Memory Organization .....................................................................................................79

9.2.1. Program Memory...................................................................................................79

9.2.2. Data Memory .........................................................................................................80

9.2.3. General Purpose Registers .....................................................................................80

9.2.4. Bit Addressable Locations .....................................................................................80

9.2.5. Stack ...................................................................................................................80

C8051F320/1

9.2.7. Register Descriptions.............................................................................................84

9.4. Power Management Modes .............................................................................................96

9.4.1. Idle Mode...............................................................................................................96

9.4.2. Stop Mode..............................................................................................................96

10. RESET SOURCES ..............................................................................................................99

10.1.Power-On Reset.............................................................................................................100

10.2.Power-Fail Reset / VDD Monitor..................................................................................101

10.4.Missing Clock Detector Reset .......................................................................................102

10.6.PCA Watchdog Timer Reset .........................................................................................102

10.7.FLASH Error Reset .......................................................................................................102

10.8.Software Reset...............................................................................................................103

C8051F320/1

14.2.Port I/O Initialization.....................................................................................................131

15.5.FIFO Management.........................................................................................................151

15.5.1. FIFO Split Mode..................................................................................................151

15.5.3. FIFO Access ........................................................................................................152

15.6.Function Addressing......................................................................................................153

15.7.Function Configuration and Control .............................................................................154

15.10.Endpoint0.....................................................................................................................161

15.10.1.Endpoint0 SETUP Transactions .........................................................................162

15.10.2.Endpoint0 IN Transactions .................................................................................162

15.10.3.Endpoint0 OUT Transactions .............................................................................163