BUCKdcdcPCBlayout_手撕buck电路资源-CSDN文库

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在设计电力电子设备时，PCB布局是至关重要的一步，尤其是对于开关电源IC，如BUCK转换器。"BUCK dcdc PCB layout"这个主题聚焦于如何有效地设计BUCK转换器的电路板布局，以确保系统的稳定性和效率。BUCK转换器是一种降压型直流-直流转换器，广泛应用于各种电源管理应用中。理解电流路径是进行正确布局的基础。如图1-a至1-c所示，当开关元件Q1导通时（图1-a），主要的电流流经CBYPASS（高频旁路电容）和CIN（大容量输入电容）。当Q1关断时（图1-b），自由轮二极管D1导通，存储在电感L中的能量被释放到输出端。在BUCK拓扑结构中，由于电感串联在输出端，因此输出电容电流变化相对平滑。图1-c则显示了Q1状态改变时，电流的剧烈波动，这些尖峰变化会在波形中引入多个谐波，是布局设计中需要特别关注的地方。进行有效的PCB布局设计，可以遵循以下步骤： 1. 输入电容和自由轮二极管应与IC终端位于同一PCB表面层，并尽可能靠近IC放置。这样可以减少走线长度，降低分布电感和电容的影响，从而减小噪声并提高瞬态响应。 2. 根据需要添加热通孔（thermal via），以改善IC的散热。这有助于降低IC的工作温度，延长其寿命，并防止因过热导致的性能下降。 3. 电感应尽可能靠近IC布置，但不必严格保持在同一层。这样可以减少电流回路的面积，降低磁耦合和辐射噪声，同时缩短布线，降低线路电阻引起的电压降。 4. 输出电容应尽可能靠近负载，以减少输出端的电压纹波。同时，输出电容的布局应考虑其对系统稳定性的影响，避免形成噪声放大器。 5. 控制信号和反馈线路的布局也至关重要。这些线路应保持短且直，以减少干扰，并确保反馈信号的准确传输。 6. 尽量使开关节点的走线短而直，以减少开关过程中产生的电磁干扰（EMI）。可以使用屏蔽或接地层来减少辐射。 7. 在可能的情况下，使用地平面或大面积的地连接，以提供低阻抗的电流路径，并帮助稳定电路。 8. 为防止噪声耦合，高电流路径和敏感信号路径应避免交叉。如果必须交叉，应在交叉点处进行适当的接地处理。 9. 在设计过程中，应进行多次仿真和测试，以验证布局是否符合预期的电气性能和EMC标准。良好的PCB布局设计对于BUCK转换器的性能至关重要。通过优化布局，可以减少噪声，提高效率，增强系统稳定性，并符合电磁兼容性要求。每个设计决策都应考虑到其对整体系统性能的影响，确保最终产品的可靠性和质量。

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1/11

No. 60AN066E Rev.003

OCTOBER 2017

Application Note

Switching Regulator Series

PCB Layout Techniques of Buck Converter

PCB layout design for switching power supply IC is as important as the circuit design. Appropriate layout can avoid various problems caused by

power supply circuit. Major problems that arise from inappropriate layout may cause increase in noise superposed by output and switching signal,

the deterioration of regulator, and also lack of stability. Adopting an appropriate layout will suppress these problems to occur.

Current Path

Figure 1-a to 1-c shows current path in a buck converter circuit.

In Figure 1-a, the red line illustrates the main current flow in the

converter when switching element Q

is ON. C

BYPASS

is a

decoupling capacitor for high frequency and C

is the capacitor

with large capacitance. The instance when the switching

element Q

is turned ON, most of the steep part of current

waveform is supplied by C

BYPASS

and then from C

In Figure 1-b, the red line illustrates the condition of current flow

when the switching element Q

is OFF. Free-wheel diode D

turns ON and energy stored in inductor L gets released to output

side. For Buck converter topology, since inductor is inserted at

output in series the output capacitor current is smooth.

Refer Figure 1-c, the red line shows the difference between

Figure 1-a and 1-b. Current in this red line changes violently

each time the switching element Q

changes from OFF to ON,

and vice versa. These sharp changes induce several harmonics

in the waveform. This difference in system needs to be paid

maximum attention during PCB layout and an important caution

point.

PCB Layout Procedure

General points of PCB layout procedure are as follows.

1. Place input capacitor and free-wheel diode on the same PCB

surface layer as the IC terminal and as close as possible to IC.

2. Include thermal via if necessary to improve heat dissipation.

3. Place inductor close to IC, no need to be as close as input

capacitor. This is to minimize radiation noise from the

switching node and do not expand copper area more than

needed.

4. Place output capacitor close to inductor.

5. Keep wiring of return path away from noise causing areas,

such as inductor and diode.

Placing of input Capacitor and Free-wheel

Diode

First of all, start placing the most important parts, such as the

input capacitor and free-wheel diode. A Single ceramic capacitor

may serve as both C

and C

BYPASS

for smaller capacitance value

of input capacitor, in designs with small current power supply

≤1A). This is because the frequency characteristics get better,

as ceramic capacitor’s capacitance value gets smaller. But

ceramic capacitor has different frequency characteristics, so

confirming it for actual parts being used is important.

As in Figure 2, when a large capacitance value capacitor is used

for C

, generally it has bad frequency characteristics. Therefore

place a decoupling capacitor C

BYPASS

for high frequency with

good frequency characteristics in parallel to C

. For C

BYPASS

use surface mount type laminated ceramic capacitor with value

of 0.1µF to 0.47µF, X5R or X7R type.

Figure 3-a shows layout example for a suitable input capacitor.

Place C

BYPASS

near IC terminal on the top layer. As in Figure 3-

b, large capacitance capacitor C

can be separated about 2cm

from C

BYPASS

that supplies most of the pulse-current. When

difficulty in space occupied, and if cannot place C

on the same

surface as IC, it can be placed at the bottom layer through via

like in Figure 3-c. Risks regarding noise can be avoided with this,

but there is a possibility of ripple-voltage to increase at high-

current, influenced by via resistance.

Figure 3-d shows the layout of C

BYPASS

and C

placed on the

reverse side. In such case, voltage noise is created by

inductance of the via, and the bypass capacitor operates as a

reverse effect. Do not carry out this kind of layout design.

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