PCIExpressV3.0-电气层规范（机翻中英对照版）

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### PCI Express V3.0-电气层规范 #### 一、概述《PCI Express V3.0-电气层规范》是一份重要的技术文档，详细介绍了PCI Express 3.0版本中的物理电气层协议。这份文档提供了中英文对照版本，便于不同语言背景的工程师和技术人员学习与理解。该规范主要用于指导PCI Express接口的设计、开发、仿真和测试工作，确保设备之间的互操作性和兼容性。 #### 二、电气层规范组织结构电气层规范在PCI Express 3.0版本中被精心组织成不同的部分，包括发射器、接收器、通道以及参考时钟(Refclk)。每个部分根据数据速率进一步划分为2.5/5.0 GT/s和8.0 GT/s两个子部分。随着数据速率的提高，参数定义和测量方法也随之变化，因此对于8.0 GT/s的数据速率，许多高频参数需要通过间接测量并结合后处理计算得出。 #### 三、互操作性标准 PCI Express 3.0的电气层规范设计确保了所有三种速度（2.5、5.0和8.0 GT/s）设备之间的向后兼容性。所有的设备都以2.5 GT/s的速率启动，因此在这个速率下可以保证互操作性。当设备协商至更高的数据速率（5.0或8.0 GT/s）运行时，则需要遵循特定的过程，这部分细节在协议部分有详细定义。 - **8.0 GT/s根端口设备**必须支持2.5、5.0和8.0 GT/s的操作，因为下游设备可能支持这些速率中的任意一种。 - **下游设备**必须至少支持2.5 GT/s，并可以选择支持5.0或8.0 GT/s，或者两者都支持。 #### 四、参考时钟(Refclk) 参考时钟(Refclk)是PCI Express 3.0电气层规范的一部分，其定义旨在确保所有三种数据速率下都能达到最小符合性的特性。这意味着即使在更高的数据速率下，也不依赖于改进Refclk的抖动特性来实现正常运行。 #### 五、参数定义与测量随着数据速率的提升，电气层规范中定义的参数及其测量方式也发生了显著变化。特别是在8.0 GT/s的数据速率下，大多数高频参数需要通过间接测量的方式获得，并通过后处理计算得到准确值。这种变化主要是为了适应高速数据传输的需求，确保在不同设备之间能够保持稳定的连接质量。 #### 六、总结 PCI Express 3.0的电气层规范对于确保高速数据传输接口的性能至关重要。通过对发射器、接收器、通道和参考时钟等关键组件进行详细规定，不仅有助于提高数据传输的效率，还能够保证不同速率设备之间的互操作性和兼容性。此外，对于那些需要进行仿真测试的学习者来说，这份文档提供了一个宝贵的资源库，可以帮助他们深入了解PCI Express 3.0的技术细节，并为实际应用提供指导。通过学习和理解PCI Express 3.0的电气层规范，工程师和技术人员可以更好地设计出符合标准的产品，从而满足市场对高性能、低延迟和高可靠性的需求。

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

323

4.3. Electrical Sub-block

4.3.1. Electrical Specification Organization

The 3.0 version of the PCI Express electrical specification is organized into separate sections for the

transmitter, receiver, the channel, and the Refclk. Each of these sections is further partitioned

according to data rate: 2.5/5.0, or 8.0 GT/s. As the data rate has evolved upward it has been

necessary to modify what parameters are defined to guarantee interoperability as well as how those

parameters are measured. For 8.0 GT/s, in particular, most high frequency parameters need to be 5

measured indirectly and then computed via postprocessing.

Due to the large differences in the parameter definition and measurement between 2.5/5.0 and

8.0 GT/s the text describing the parameters is located in separate subsections. Where parameters are

common among all three data rates, they appear in a single table with columns for each of the three

data rates.

4.3.2. Interoperability Criteria for 2.5, 5.0, and 8.0 GT/s

Devices

The PCI Express electrical specification is constructed to guarantee backwards compatibility among

devices of all three speeds. Since all devices power up at 2.5 GT/s interoperability at that speed is

guaranteed. Operation at 5.0 or 8.0 GT/s requires that the two devices negotiate to a higher data

rate. Details of this process are defined in the protocol section.

8.0 GT/s root Port devices must support 2.5, 5.0, and 8.0 GT/s operation, because a downstream 15

device could support any of these data rates. A downstream device must support 2.5 GT/s and may,

support either 5.0 or 8.0 GT/s operation, or both.

The Refclk is defined as part of the 3.0 electrical specification with the expectation that the

characteristics which define a minimally compliant Refclk are approximately the same for all three

data rates. In other words, operation at the higher data rates is not predicated upon improving the

jitter characteristics of the Refclk.

Data rates of 5.0 GT/s and 8.0 GT/s specify a procedure for tolerancing the channel, where the

characteristics of a minimally compliant channel for 5.0 and 8.0 GT/s are approximately the same.

4.3.2.1.

8.0 GT/s Standards Applied to 2.5 and 5.0 GT/s Devices

Evolving process technology and circuit characteristics which enable 8.0 GT/s performance

imposes limitations on a small number of parameters defined for 2.5 and 5.0 GT/s operation. The

merged 2.5/5.0/8.0 GT/s specification addresses these limitations by relaxing or extending certain

2.5 and 5.0 GT/s parameters. These changes are also reflected in the relevant parameter tables.

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

324

4.3.2.1.1. ESD Standards

All PCI Express signal and power supply pins must be tested for ESD protection levels to the

Human Body Model (HBM) and the Charged Device Model (CDM) standards in accordance with

ESDA/JEDEC JS-001-2010 (for HBM) and in accordance with JEDEC JESD22-C101 (for CDM).

Pins must meet or exceed the minimum levels recommended in JEDEC JEP155/JEP157

(HBM/CDM) or JEDEC approved superseding documents. Note that this section is applicable for 5

2.5, 5.0, and 8.0 GT/s capable devices.

4.3.2.1.2. Receiver Powered Off Resistance

The Z

RX-HIGH-IMP-DC-POS

and Z

RX-HIGH-IMP-DC-NEG

parameter values defined for 8.0 GT/s will be applied

to 2.5 and 5.0 GT/s devices.

4.3.2.1.3.

Tx Equalization Tolerance

The tolerance for TxEQ de-emphasis for 2.5 and 5.0 GT/s signaling is relaxed from ±0.5 dB to

±1.0 dB. This change makes the -3.5 and -6.0 dB de-emphasis tolerance consistent for all three data 10

rates.

4.3.2.1.4.

Tx Equalization During Tx Margining

The 2.5 and 5.0 GT/s specifications state that the ±0.5 dB TxEQ tolerance is relaxed to ±1.0 dB

during Tx margining. For 8.0 GT/s, the accuracy that can be achieved for TxEQ settings is

determined by the Tx coefficient granularity and the TxEQ tolerances specified for the transmitter

during normal operation. 15

4.3.2.1.5. V

TX-ACCM

and V

RX-ACCM

For 8.0 GT/s both the Tx ACCM and the Rx ACCM limits have changed with respect to those

defined for 2.5 GT/s and 5.0 GT/s. For both 2.5 and 5.0 GT/s, V

TX-ACCM

is relaxed to 150 mVPP,

but a separate LF component is not defined.

Rx AC CM limit of 300 mVPP for 2.5/5.0 GT/s remains unchanged. The 8.0 GT/s AC CM limits

are defined in Section 4.3.4.4.1 and Table 4-22.

4.3.2.2.

2.5 GT/s is Not a Subset of 5.0 GT/s and 5.0 GT/s is Not

a Subset of 8.0 GT/s

Since a 5.0 GT/s device must be capable of operation at either 2.5 GT/s or 5.0 GT/s data rates, the

device must meet the 2.5 GT/s and 5.0 GT/s specifications in their entirety. Meeting only the

5.0 GT/s specification does not guarantee interoperability at 2.5 GT/s speeds, as is described in the

following example.

The 5.0 GT/s clock specification requires a tighter window than 2.5 GT/s (8-16 MHz vs. 1.5-22 25

MHz). Imagine a clock source that just meets the 5.0 GT/s Refclk jitter specification, but has a

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

325

huge jitter spike at 3 MHz (or 20 MHz). This spike would not be caught by the 8-16 MHz range,

but could potentially fail the 2.5 GT/s component. Therefore, the clocks need to pass both the

2.5 GT/s and 5.0 GT/s limits.

4.3.2.3.

Component Interfaces

PCI Express components from different manufacturers must interoperate reliably together. At the

electrical level, this is achieved by specifying a set of parameters and the interfaces at which those 5

parameters must be met. For 5.0 GT/s PCI Express components, this interface is defined to be at

the pins of the Receiver and Transmitter devices and the corresponding locations at either end of

the channel. At 2.5 GT/s the requirement to reference all measurements to the Tx or Rx pins is less

explicitly stated in the specification, but still holds true. The pin location was also chosen because it

permits a component to be characterized independently of others. For example, a Transmitter can

be measured without needing any other PCI Express components.

A-0543

Transmitter Receiver

Refclk

Pins

Tx Pins

Refclk

Pins

Rx Pins

Refclk

Channel

Figure 4-31: Transmitter, Channel, and Receiver Boundaries

Additional interfaces may be specified at the connector or connectors for multi-segment topologies,

such as between server blades and backplane or between a motherboard and adapter. Due to the 15

large number of possible combinations and their product specific nature, multi-segment

specifications will be detailed in the PCI Express Card Electromechanical Specification and other form

factor specifications.

4.3.3. Transmitter Specification

4.3.3.1.

Transmitter Pin to Pad Correlation

The PCI Express Specification defines Transmitter and Receiver measurements at the pin, while a

pad location is preferred by silicon designers. Measurements to specification are referenced to a 20

device’s pins, because this is the only location that is generally accessible for probing (die-pads in an

assembled device are not usually accessible). It is the shared responsibility of the silicon and the

package designers to account for silicon package interactions and guarantee positive margins at the

device's pins.

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