UM10800
LPC82x User manual
Rev. 1 — 18 September 2014 User manual
Document information
Info Content
Keywords LPC82x, LPC824M201JHI33, LPC822M101JHI33, LPC824M201JDH20,
LPC822M101JDH20, LPC82x UM, LPC82x user manual, LPC820
Abstract LPC82x User manual
UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
User manual Rev. 1 — 18 September 2014 2 of 485
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For more information, please visit: http://www.nxp.com
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NXP Semiconductors
UM10800
LPC82x User manual
Revision history
Rev Date Description
1 20140918 Initial revision. LPC82x User manual.
UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
User manual Rev. 1 — 18 September 2014 3 of 485
1.1 Introduction
The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and
8 KB of SRAM.
The peripheral complement of the LPC82x includes a CRC engine, four I
2
C-bus
interfaces, up to three USARTs, up to two SPI interfaces, one multi-rate timer,
self-wake-up timer, and state-configurable timer with PWM function (SCTimer/PWM), a
DMA, one 12-bit ADC and one analog comparator, function-configurable I/O ports through
a switch matrix, an input pattern match engine, and up to 29 general-purpose I/O pins.
Remark: For additional documentation, see Section 35.2 “
References”.
1.2 Features
• System:
– ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to
30 MHz with single-cycle multiplier and fast single-cycle I/O port.
– ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
– System tick timer.
– AHB multilayer matrix.
– Serial Wire Debug (SWD) with four break points and two watch points. JTAG
boundary scan (BSDL) supported.
– Micro Trace Buffer (MTB)
• Memory:
– Up to 32 KB on-chip flash programming memory with 64 Byte page write and
erase. Code Read Protection (CRP) supported.
– 8 KB SRAM.
• ROM API support:
– bootloader.
– On-chip ROM APIs for ADC, SPI, I2C, USART, power configuration (power
profiles) and integer divide.
– Flash In-Application Programming (IAP) and In-System Programming (ISP).
• Digital peripherals:
– High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to
32 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, input inverter, and glitch filter. GPIO direction
control supports independent set/clear/toggle of individual bits.
– High-current source output driver (20 mA) on four pins.
– High-current sink driver (20 mA) on two true open-drain pins.
UM10800
Chapter 1: LPC82x Introductory information
Rev. 1 — 18 September 2014 User manual
UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
User manual Rev. 1 — 18 September 2014 4 of 485
NXP Semiconductors
UM10800
Chapter 1: LPC82x Introductory information
– GPIO interrupt generation capability with boolean pattern-matching feature on
eight GPIO inputs.
– Switch matrix for flexible configuration of each I/O pin function.
– CRC engine.
– DMA with 18 channels and 9 trigger inputs.
• Timers:
– State Configurable Timer (SCTimer/PWM) with input and output functions
(including capture and match) for timing and PWM applications.
– Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to
four programmable, fixed rates.
– Self-Wake-up Timer (WKT) clocked from either the IRC, a low-power,
low-frequency internal oscillator, or an external clock input in the always-on power
domain.
– Windowed Watchdog timer (WWDT).
• Analog peripherals:
– One 12-bit ADC with up to 12 input channels with multiple internal and external
trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports
two independent conversion sequences.
– Comparator with four input pins and external or internal reference voltage.
• Serial peripherals:
– Three USART interfaces with pin functions assigned through the switch matrix and
one common fractional baud rate generator.
– Two SPI controllers with pin functions assigned through the switch matrix.
– Four I
2
C-bus interfaces. One I2C supports Fast-mode plus with 1 Mbit/s data rates
on two true open-drain pins and listen mode. Three I2Cs support data rates up to
400 kbit/s on standard digital pins.
• Clock generation:
– 12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be
used as a system clock.
– Crystal oscillator with an operating range of 1 MHz to 25 MHz.
– Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
– PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator, the external clock
input, or the internal RC oscillator.
– Clock output function with divider that can reflect all internal clock sources.
• Power control:
– Integrated PMU (Power Management Unit) to minimize power consumption.
– Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode.
– Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI,
and I2C peripherals.
– Timer-controlled self-wake-up from Deep power-down mode.
– Power-On Reset (POR).
UM10800 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
User manual Rev. 1 — 18 September 2014 5 of 485
NXP Semiconductors
UM10800
Chapter 1: LPC82x Introductory information
– Brownout detect (BOD).
• Unique device serial number for identification.
• Single power supply (1.8 V to 3.6 V).
• Operating temperature range -40 °C to +105 °C.
• Available in a HVQFN33 (5x5) package.
1.3 Ordering options
1.4 General description
1.4.1 ARM Cortex-M0+ core configuration
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in
the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points.
The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO
access at address 0xA000 0000. The ARM Cortex M0+ core version is r0p1.
The core includes a single-cycle multiplier and a system tick timer (SysTick).
Table 1. Ordering information
Type number Package
Name Description Version
LPC824M201JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 5 5 0.85 mm
n/a
LPC822M101JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 5 5 0.85 mm
n/a
LPC824M201JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
LPC822M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Table 2. Ordering options
Type number Flash/
KB
SRAM/
KB
USART I
2
C SPI ADC
channels
Comparator GPIO Package
LPC824M201JHI33 32 8 3 4 2 12 Y 29 HVQFN33
LPC822M101JHI33 16 4 3 4 2 12 Y 29 HVQFN33
LPC824M201JDH20 32 8 3 4 2 5 Y 16 TSSOP20
LPC822M101JDH20 16 4 3 4 2 5 y 16 TSSOP20
