UM10375
LPC1311/13/42/43 User manual
Rev. 01 — 6 November 2009 User manual
Document information
Info Content
Keywords ARM Cortex-M3, microcontroller, USB, LPC1311, LPC1313, LPC1342,
LPC1343
Abstract LPC1311/13/42/43 user manual
UM10375_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 01 — 6 November 2009 2 of 305
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors
UM10375
LPC13xx preliminary UM
Revision history
Rev Date Description
01 20091105 LPC1311/13/42/43 user manual
UM10375_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 01 — 6 November 2009 3 of 305
1. Introduction
The LPC13xx are ARM Cortex-M3 based microcontrollers for embedded applications
featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC13xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC13xx series includes up to 32 kB of flash memory,
up to 8 kB of data memory, USB Device, one Fast-mode Plus (FM+) I
2
C interface, one
UART, four general purpose timers, and up to 42 general purpose I/O pins.
2. How to read this manual
This user manual describes parts LPC1311, LPC1313, LPC1342, LPC1343. Part-specific
features and registers are listed at the beginning of each chapter.
3. Features
• ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
• Up to 32 kB on-chip flash programming memory.
• In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
• Up to 8 kB of on-chip static SRAM.
• Serial interfaces:
– USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43
only).
– UART with fractional baud rate generation, internal FIFO and RS-485/EIA-485
support, and modem control.
– SSP controller with FIFO and multi-protocol capabilities.
– I
2
C-bus interface supporting the full I
2
C-bus specification and Fast-mode Plus with
a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
• Other peripherals:
– Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors.
– High-current output driver (20 mA) on one pin.
– High-current sink drivers (20 mA) on two I
2
C-bus pins in Fast-mode Plus.
UM10375
Chapter 1: LPC13xx Introductory information
Rev. 01 — 6 November 2009 User manual
UM10375_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 01 — 6 November 2009 4 of 305
NXP Semiconductors
UM10375
Chapter 1: LPC13xx Introductory information
– Four general purpose timers/counters, with a total of four capture inputs and 13
compare outputs.
– Watchdog Timer (WDT).
– System tick timer.
• Serial Wire Debug and Serial Wire Trace Port.
• Integrated PMU (Power Management Unit) automatically adjusts internal regulators to
minimize power consumption during Sleep, Deep-sleep, and Deep power-down
modes.
• Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
• Single 3.3 V power supply (2.0 V to 3.6 V).
• 10-bit ADC with input multiplexing among 8 pins.
• GPIO pins can be used as edge and level sensitive interrupt sources.
• Clock output function with divider that can reflect the main oscillator clock, IRC clock,
CPU clock, or the Watchdog clock.
• Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40
pins.
• Brownout detect with four separate thresholds for interrupt and one threshold for
forced reset.
• Power-On Reset (POR).
• Crystal oscillator with an operating range of 1 MHz to 25 MHz.
• 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
a system clock.
• PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the Watchdog oscillator.
• Available in LQFP48 and HVQFN33 packages.
4. Ordering options
Table 1. Ordering options for the LPC13xx parts
Type number Flash Total
SRAM
USB UART
RS-485
I
2
C/
Fast+
SSP ADC
channels
Pins Package
LPC1311FHN33 8 kB 4 kB - 1 1 1 8 33 HVQFN33
LPC1313FBD48 32 kB 8 kB - 1 1 1 8 48 LQFP48
LPC1313FHN33 32 kB 8 kB - 1 1 1 8 33 HVQFN33
LPC1342FHN33 16 kB 4 kB Device 1 1 1 8 33 HVQFN33
LPC1343FBD48 32 kB 8 kB Device 1 1 1 8 48 LQFP48
LPC1343FHN33 32 kB 8 kB Device 1 1 1 8 33 HVQFN33
UM10375_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 01 — 6 November 2009 5 of 305
NXP Semiconductors
UM10375
Chapter 1: LPC13xx Introductory information
5. Block diagram
(1) LPC1342/43 only.
(2) LQFP48 package only.
Fig 1. LPC13xx block diagram
SRAM
4/8 kB
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
FLASH
8/16/32 kB
USB DEVICE
CONTROLLER
(1)
I-code
bus
D-code
bus
system
bus
AHB TO
APB
BRIDGE
HIGH-SPEED
GPIO
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTALIN
XTALOUT
RESET
clocks and
controls
SWD
USB PHY
(1)
SSP 10-bit ADC
UART
I
2
C
32-bit COUNTER/TIMER 0/1
WDT
IOCONFIG
LPC1311/13/42/43
slave
002aae722
slaveslave
slave
slave
ROM
slave
AHBLite BUS
GPIO ports
PIO0/1/2/3
SCK
SSEL
MISO
MOSI
4/4 × MAT
AD[7:0]
1/1 × CAP
SDA
SCL
RXD
TXD
DTR, DSR
(2)
, CTS,
DCD
(2)
, RI
(2)
, RTS
SYSTEM CONTROL
16-bit COUNTER/TIMER 0/1
3/2 × MAT
1/1 × CAP
USB pins
CLKOUT
IRC
POR
