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jc404^20170212^316.12^IBM^OpenCAPI_DDR5_Differential_Interface.p...
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2019-05-25
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OpenCAPI asDDR5 Differential Interface, OpenCAPIis an Open Interface Architecture that allows any microprocessor (agnostic to processor architecture) to attach to coherent user-level accelerators, I/O devices and advanced memories (via read/write or user-level DMA semantics)
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OpenCAPI as
DDR5 Differential Interface
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JC40 Item# 316.12
JC45 Item# 2256.09
JC16 Item# 154.02
IBM
Feb. 12, 2017
Differential Host Interface
‣ Propose to adopt subset of OpenCAPI
spec optimized to memory access as the
differential host interface spec
– CAPI: Coherent Accerelator Processor Interface
OpenCAPI
‣ OpenCAPI is an Open Interface Architecture that allows
any microprocessor (agnostic to processor architecture) to
attach to coherent user-level accelerators, I/O devices and
advanced memories (via read/write or user-level DMA
semantics)
‣ OpenCAPI LPC mode
– Low latency
– Specifically designed for memory access
– Functional for deterministic, non-deterministic and
potential near memory processing applications (aka,
types I, II and III)
‣ Subset of the OpenCAPI specification to be provided
to JEDEC by the OpenCAPI Consortium, to be subset
of JEDEC standard (working)
OpenCAPI/JEDEC collaboration (example)
‣ JEDEC members to be allowed to use the spec for free (for
memory attached devices)
‣ Control point for all of OpenCAPI specification will be
within the OpenCAPI Consortium
‣ Any changes requested to help the JEDEC standard to be
requested in the appropriate OpenCAPI WG (through
JEDEC TG)
‣ RAND, etc. to be clearly defined between two bodies to
guarantee no IP legal issues
‣ MOU needed between the OpenCAPI Consortium and
JEDEC to document these arrangements (working)
Background - Key Attributes of OpenCAPI
‣ High-bandwidth, low latency interface optimized to enable
streamlined implementation of attached devices
– 25Gbps signaling and protocol built to enable very low latency
interface on CPU and attached device
– Complexities of coherence and virtual addressing implemented on
host microprocessor to simplify attached devices and facilitate
interoperability across multiple CPU architectures
‣ Attached devices operate natively within an application’s user
space and coherently with processors
– Allows attached device to fully participate in application without
kernel involvement/overhead
‣ Supports a wide range of use cases and access semantics
– Hardware accelerators, high-performance I/O devices, advanced
memories
‣ 100% Open Consortium / All company participants welcome /
All ISA participants welcome
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