+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; sintalbe625A_inst|altsyncram_component|auto_generated ; 11 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; sintalbe625A_inst ; 11 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
基于fpga的正弦信号发生器verilog代码 （681个子文件） 
_deps 736B _info 21KB _info 12KB _info 10KB _info 9KB _info 8KB _info 5KB _info 1KB ._verilog_libs_altera_lnsim_ver__info 9KB ._verilog_libs_altera_mf_ver__info 21KB ._verilog_libs_altera_ver__info 10KB ._verilog_libs_cycloneiii_ver__info 12KB ._verilog_libs_lpm_ver__info 8KB ._verilog_libs_sgate_ver__info 5KB ._verilog_libs_altera_mf_ver_@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s_fast.asm 322KB ._verilog_libs_altera_mf_ver_@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n_fast.asm 231KB ._verilog_libs_altera_mf_ver_altsyncram_fast.asm 116KB rtl_work_sin_fast.asm 26KB rtl_work_sintalbe625_fast.asm 9KB rtl_work_test_tb_fast.asm 4KB sin.v.bak 42KB sin_run_msim_rtl_verilog.do.bak 2KB test_tb.v.bak 412B sin_run_msim_rtl_verilog.do.bak1 2KB sin_run_msim_rtl_verilog.do.bak10 2KB sin_run_msim_rtl_verilog.do.bak11 2KB sin_run_msim_rtl_verilog.do.bak2 2KB sin_run_msim_rtl_verilog.do.bak3 2KB sin_run_msim_rtl_verilog.do.bak4 2KB sin_run_msim_rtl_verilog.do.bak5 2KB sin_run_msim_rtl_verilog.do.bak6 2KB sin_run_msim_rtl_verilog.do.bak7 2KB sin_run_msim_rtl_verilog.do.bak8 2KB sin_run_msim_rtl_verilog.do.bak9 2KB sin.cmp.bpm 879B sin.map.bpm 864B sintalbe1024.bsf 3KB sintalbe625.bsf 3KB sin.cmp.cdb 70KB sin.root_partition.cmp.cdb 28KB sin.sgdiff.cdb 23KB sin.rtlv_sg.cdb 21KB sin.(0).cnf.cdb 20KB sin.map.cdb 19KB sin.root_partition.map.cdb 19KB sin.pre_map.cdb 19KB sin.idb.cdb 10KB sin.(3).cnf.cdb 3KB sin.rtlv_sg_swap.cdb 2KB sin.(1).cnf.cdb 2KB sin.(5).cnf.cdb 1KB sin.(4).cnf.cdb 1KB sin.(2).cnf.cdb 1KB sin.(6).cnf.cdb 1KB sin.(8).cnf.cdb 1KB sin.(7).cnf.cdb 1KB sin.map_bb.cdb 1KB sin.root_partition.map.hbdb.cdb 876B sin.amm.cdb 563B _primary.dat 147KB _primary.dat 83KB _primary.dat 79KB _primary.dat 72KB _primary.dat 67KB _primary.dat 67KB _primary.dat 67KB _primary.dat 65KB _primary.dat 54KB _primary.dat 39KB _primary.dat 37KB _primary.dat 37KB _primary.dat 28KB _primary.dat 25KB logic_util_heursitic.dat 24KB _primary.dat 23KB _primary.dat 23KB _primary.dat 22KB _primary.dat 19KB _primary.dat 19KB _primary.dat 15KB _primary.dat 14KB _primary.dat 12KB _primary.dat 11KB _primary.dat 11KB _primary.dat 10KB _primary.dat 10KB _primary.dat 10KB _primary.dat 10KB _primary.dat 10KB _primary.dat 9KB _primary.dat 8KB _primary.dat 8KB _primary.dat 7KB _primary.dat 7KB _primary.dat 6KB _primary.dat 6KB _primary.dat 6KB _primary.dat 6KB _primary.dat 5KB _primary.dat 5KB共 681 条
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资源评论
qingaotian2018-02-06不错的资料
失去梦想的鸡腿2018-05-19为什么Windows要报病毒？ 编译到一半quartusII报错？ 是我quartus版本不对吗？
Aliluyo2016-11-13谢谢分享，是个好资料，能够运行
