CH7025_CH7026PrelimFullDatasheetRev1.1.pdf资源-CSDN文库

需积分: 16 108 浏览量 2013-03-27 13:13:16 上传评论收藏 867KB PDF 举报

CH7025/CH7026是一款适用于便携式及其他类似消费者系统的视频/图形编码器，其主要功能是接收数字输入信号，通过10位数字模拟转换器（DACs）编码并传输数据。该设备能够对视频信号进行编码，并生成适用于NTSC和PAL标准的SDTV格式同步信号，以及480p、576p、720p和1080i的HDTV格式同步信号。除了标准的复合同步信号输出外，它还支持模拟RGB输出和复合视频同步信号（SYNC）输出。CH7025/CH7026支持多种数据格式输入，包括RGB和YCbCr（例如RGB565、RGB666、RGB888、类似ITU656的YCbCr等），并且支持隔行扫描和逐行扫描的输入数据格式。设备内置了16Mbit的SDRAM，用作帧缓冲区，支持帧率转换，图像旋转、缩放和拉伸功能。在特性方面，CH7025/CH7026支持多种输出格式，包括SDTV格式（NTSC和PAL）、480p、576p、720p和1080i的HDTV格式、VGA的模拟RGB输出以及可编程合成或分离方式输出的同步信号。设备内置了三个10位高速DAC，提供了灵活的输出能力，可以实现单、双、三路复合视频基色信号（CVBS）输出，YPbPr输出，RGB输出，以及CVBS和S视频输出的同步进行。内置的16Mbit SDRAM作为帧缓冲区使用，并且支持帧率转换，90度、180度、270度的图像旋转以及垂直或水平的翻转功能。该设备还具备可编程的24位/18位/16位/15位/12位/8位数字输入接口，支持多种RGB（RGB888、RGB666、RGB565等）、YCbCr（4:4:4 YCbCr、ITU656）和2x或3x复用输入。CPU/内存接口也得到了支持，输入分辨率的灵活性支持高达800x800和1024x680，同时320x240、640x480、960x720等分辨率也得到支持。此外，设备提供了旁通模式，并内置了灵活的上下缩放引擎，具备去闪烁功能以及文本增强支持。设备对每种输出形式均支持逐像素的亮度、对比度、色调和饱和度调整，对RGB输出则只支持亮度和对比度调整。此外，逐像素水平位置调整和逐行垂直位置调整也得到了支持。通过串行端口可以对设备进行完全编程，IO以及SPC/SPD电压也得到支持。综合上述描述，CH7025/CH7026是一款多功能的视频编码器，适用于多种视频标准和输入输出格式，内置的SDRAM帧缓冲区使其具备处理高分辨率和高帧率视频信号的能力。其内置的DAC和多种编程接口使得设备在处理不同信号源和输出至不同显示设备时具备了极高的灵活性。图像处理功能如旋转、缩放、去闪烁和文本增强等，进一步增强了该设备在视频处理领域的实用性。此外，设备的编程能力和多种调整功能使其可以广泛应用于需要图形处理的消费者电子设备中。

资源推荐

资源详情

资源评论

CH7025/CH7026 Datasheet

201-1000-001 Rev. 1.1 2008-08-18

Chronte

Chrontel CH7025/CH7026 TV/VGA Encoder

Features General Description

• Support multiple output formats. Such as SDTV format

(NTSC and PAL), HDTV format for 480p,576p,720p and

1080i, analog RGB output for VGA. Sync signals can be

provided in separated or composite manner (Programmable

composite sync generation).

• Three on-chip 10-bit high speed DACs providing flexible

output capabilities. Such as single, double or triple CVBS

outputs, YPbPr output, RGB output and simultaneous CVBS

and S-video outputs.

• Internal embedded 16Mbits SDRAM is used as frame buffer.

Supporting for frame rate conversion. 90/180/270 degree

image rotation and vertical or horizontal flip functions are

supported.

• Programmable 24-bit/18-bit/16-bit/15-bit/12-bit/8-bit digital

input interface supports various RGB (RGB888, RGB666,

RGB565 and etc), YCbCr (4:4:4 YCbCr, ITU656) and 2x or

3x multiplexed input. CPU/Memory interface are supported.

• Support for flexible input resolution is up to 800x800 and

1024x680. 320x240, 640x480, 960x720 are support.

• Bypass mode is supported.

• Flexible up and down scaling engine is embedded including

de-flickering capability. Text enhancement is supported.

• Pixel by pixel brightness, contrast, hue and saturation

adjustment for each kind of output are supported. For RGB

output, only brightness and contrast adjustment are

supported.

• Pixel by pixel horizontal position adjustment and line by line

vertical position adjustment are supported.

• Fully programmable through serial port. IO and SPC/SPD

voltage supported is from 1.2V to 3.3V.

• TV/Monitor connection detect capability.

• Programmable power management. DAC can be switched off

based on detection result (Driver support is required).

• Flexible pixel clock frequency from graphics controller is

supported (2.3MHz –120MHz). Flexible input clock from

crystal or oscillator is supported (2.3MHz – 64MHz).

• Macrovision

7.1.L1 for SDTV is supported in CH7025

(CH7026 is Non-Macrovision part.). Macrovision

copy

protection support for progressive scan TV (480p, 576p

CH7025 only).

• CGMS-A support for SDTV and HDTV (CH7025 only).

• Offered in BGA or QFP package.

The CH7025/CH7026 is a device targeting handheld

and similar consumer systems which accept digital

input signal. CH7025/CH7026 encodes and transmits

data through 10-bit DACs. The device is able to

encode the video signals and generate synchronization

signals SDTV format for NTSC and PAL standards

and HDTV format for 480p,576p,720p and 1080i.

Analog RGB output and composite SYNC signal are

also supported. The device accepts different data

formats including RGB and YCbCr (e.g. RGB565,

RGB666, RGB888, ITU656 like YCbCr, etc.).Both

interlaced and non-interlaced input data formats are

supported. 16Mbit SDRAM is embedded in package.

Frame rate conversion, Image rotation, zooming and

scaling, are supported.

Note: the above feature list is subject to change without notice. Please contact Chrontel for more information

and current updates.

CHRONTEL CH7025/CH7026 Datasheet

201-1000-001 Rev. 1.1 2008-08-18

TABLE OF CONTENTS

1.0 Pin-out ...........................................................................................................................................................5

1.1 Package Diagram.......................................................................................................................................5

1.2 Pin Description ..........................................................................................................................................6

2.0 Functional Description.................................................................................................................................10

2.1 Input Interface..........................................................................................................................................10

2.1.1 Overview..........................................................................................................................................10

2.1.2 Input Clock and Data Timing Diagram............................................................................................10

2.1.3 Input Data Voltage...........................................................................................................................11

2.1.4 Input Data Format............................................................................................................................11

2.2 Chip Output .............................................................................................................................................13

2.2.1 TV Output........................................................................................................................................13

2.2.2 VGA Output.....................................................................................................................................14

2.2.3 Video DAC Output ..........................................................................................................................14

2.2.4 DAC Single/Double Termination ....................................................................................................14

2.2.5 Video DAC Connection Detect .......................................................................................................14

2.2.6 Picture Enhancement .......................................................................................................................14

2.2.7 Color Sub-carrier Generation...........................................................................................................14

2.2.8 ITU-R BT.470 Compliance .............................................................................................................15

2.3 Testing Functions and Power Down Mode..............................................................................................15

2.3.1 Test Pattern Select ...........................................................................................................................15

2.3.2 SDRAM Power Down .....................................................................................................................15

3.0 Register Control...........................................................................................................................................16

3.1 Control Registers Index ...........................................................................................................................16

3.2 Control Registers Map.............................................................................................................................19

3.3 Register Descriptions...............................................................................................................................22

4.0 Electrical Specifications ..............................................................................................................................50

4.1 Absolute Maximum Ratings ....................................................................................................................50

4.2 Recommended Operating Conditions......................................................................................................50

4.3 Electrical Characteristics .........................................................................................................................51

4.4 Digital Inputs / Outputs............................................................................................................................51

4.5 AC Specifications ....................................................................................................................................52

5.0 Package Dimensions....................................................................................................................................53

6.0 Revision History ..........................................................................................................................................55

CHRONTEL CH7025/CH7026 Datasheet

201-1000-001 Rev. 1.1 2008-08-18

FIGURES AND TABLES

List of Figures

Figure 1: CH7025/CH7026 Block Diagram ..................................................................................................................2

Figure 2: BGA Package (Top View) .............................................................................................................................5

Figure 3: 80 Pin LQFP Package ....................................................................................................................................6

Figure 4: Clock and Data Input Timing in 3x Multiplexed Mode ..............................................................................10

Figure 5: SDR and DDR Input Data Formats..............................................................................................................10

Figure 6: Horizontal Input Timing ..............................................................................................................................11

Figure 7: Vertical Input Timing...................................................................................................................................11

Figure 8: CPU/MEMORY Interface Timing ...............................................................................................................11

Figure 9: 80 Pin BGA Package....................................................................................................................................53

Figure 10: 80 Pin LQFP Package ................................................................................................................................54

List of Tables

Table 1: Pin Name Description (BGA Package) ...........................................................................................................6

Table 2: Pin Name Descriptions (LQFP80 Package) ....................................................................................................8

Table 3: Input Data Format.........................................................................................................................................12

Table 4: Supported SDTV Standards...........................................................................................................................13

Table 5: Supported EDTV/HDTV Standards ..............................................................................................................13

Table 6: Composite Sync Type....................................................................................................................................14

Table 7: Video DAC Configurations for CH7025/CH7026 ........................................................................................14

Table 8: Test Pattern Selection....................................................................................................................................15

Table 9: Control Registers Index.................................................................................................................................16

Table 10: Serial Port Register Map..............................................................................................................................19

Table 11 : DAC Power Down Control Bits .................................................................................................................23

Table 12: Multiple TV Output Configuration..............................................................................................................25

Table 13: DAC Output Swapping Sequence ...............................................................................................................25

Table 14 : HIGH,SWAP Format .................................................................................................................................26

Table 15: SDTV/VGA Output Format ........................................................................................................................26

Table 16: Macrovision Level Mode MVMODE[1:0]..................................................................................................41

Table 17 : EDTV/HDTV Output Format.....................................................................................................................43

Table 18: Attached Display Mapping..........................................................................................................................49