CMSIS.zip_stm32F103C8T6开发_stm32f_stm32f103c8t6_zip

/** ****************************************************************************** * @file system_stm32f10x.c * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * @author STMicroelectronics - MCD Application Team * @version V3.0.0 * @date 04/06/2009 ****************************************************************************** * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2> ****************************************************************************** */ /** @addtogroup Private_Includes * @{ */ #include "stm32f10x.h" /** * @} */ /** @addtogroup Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup Private_Defines * @{ */ /*!< Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after reset the HSI is used as SYSCLK source) */ //#define SYSCLK_FREQ_HSE HSE_Value //#define SYSCLK_FREQ_20MHz 20000000 //#define SYSCLK_FREQ_36MHz 36000000 //#define SYSCLK_FREQ_48MHz 48000000 //#define SYSCLK_FREQ_56MHz 56000000 #define SYSCLK_FREQ_72MHz 72000000 /*!< Uncomment the following line if you need to use external SRAM mounted on STM3210E-EVAL board (STM32 High density devices) as data memory */ #ifdef STM32F10X_HD /* #define DATA_IN_ExtSRAM */ #endif /* STM32F10X_HD */ /** * @} */ /** @addtogroup Private_Macros * @{ */ /** * @} */ /** @addtogroup Private_Variables * @{ */ /******************************************************************************* * Clock Definitions *******************************************************************************/ #ifdef SYSCLK_FREQ_HSE const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */ #elif defined SYSCLK_FREQ_20MHz const uint32_t SystemFrequency = SYSCLK_FREQ_20MHz; /*!< System Clock Frequency (Core Clock) */ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_20MHz; /*!< System clock */ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_20MHz; /*!< AHB System bus speed */ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_20MHz; /*!< APB Peripheral bus 1 (low) speed */ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_20MHz; /*!< APB Peripheral bus 2 (high) speed */ #elif defined SYSCLK_FREQ_36MHz const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */ #elif defined SYSCLK_FREQ_48MHz const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */ #elif defined SYSCLK_FREQ_56MHz const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */ #elif defined SYSCLK_FREQ_72MHz const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */ #else /*!< HSI Selected as System Clock source */ const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */ const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */ const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */ const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */ const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */ #endif /** * @} */ /** @addtogroup Private_FunctionPrototypes * @{ */ static void SetSysClock(void); #ifdef SYSCLK_FREQ_HSE static void SetSysClockToHSE(void); #elif defined SYSCLK_FREQ_20MHz static void SetSysClockTo20(void); #elif defined SYSCLK_FREQ_36MHz static void SetSysClockTo36(void); #elif defined SYSCLK_FREQ_48MHz static void SetSysClockTo48(void); #elif defined SYSCLK_FREQ_56MHz static void SetSysClockTo56(void); #elif defined SYSCLK_FREQ_72MHz static void SetSysClockTo72(void); #endif /** * @} */ /** @addtogroup Private_Functions * @{ */ /** * @brief Setup the microcontroller system * Initialize the Embedded Flash Interface, initialize the PLL and update th SystemFrequency variable * @param None. * @arg None. * @note : This function should be used only after reset. * @retval value: None. */ void SystemInit (void) { /*!< RCC system reset(for debug purpose) */ /*!< Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */ RCC->CFGR &= (uint32_t)0xF8FF0000; /*!< Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /*!< Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /*!< Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; /*!< Disable all interrupts */ RCC->CIR = 0x00000000; /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /*!< Configure the Flash Latency cycles and enable prefetch buffer