BLDC_HALL.zip_BLDC HALL _BLDC STM32_STM32_BLDC_bldc stm32_stm3

; generated by ARM C/C++ Compiler, 5.03 [Build 76] ; commandline ArmCC [--list --debug -c --asm --interleave -o.\stm32f0xx_i2c.o --asm_dir=.\ --list_dir=.\ --depend=.\stm32f0xx_i2c.d --cpu=Cortex-M0 --apcs=interwork -O0 -I.\Include -I"D:\MySelf\STM32F030 Diary\BLDC_HALL\RTE" -IC:\Keil\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS\Include -IC:\Keil\ARM\PACK\Keil\STM32F0xx_DFP\1.0.0\Device\Include -D_RTE_ -DSTM32F030X8 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX --omf_browse=.\stm32f0xx_i2c.crf Source\stm32f0xx_i2c.c] THUMB AREA ||.text||, CODE, READONLY, ALIGN=2 I2C_DeInit PROC ;;;144 */ ;;;145 void I2C_DeInit(I2C_TypeDef* I2Cx) 000000 b510 PUSH {r4,lr} ;;;146 { 000002 4604 MOV r4,r0 ;;;147 /* Check the parameters */ ;;;148 assert_param(IS_I2C_ALL_PERIPH(I2Cx)); ;;;149 ;;;150 if (I2Cx == I2C1) 000004 48f9 LDR r0,|L1.1004| 000006 4284 CMP r4,r0 000008 d109 BNE |L1.30| ;;;151 { ;;;152 /* Enable I2C1 reset state */ ;;;153 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); 00000a 2101 MOVS r1,#1 00000c 0548 LSLS r0,r1,#21 00000e f7fffffe BL RCC_APB1PeriphResetCmd ;;;154 /* Release I2C1 from reset state */ ;;;155 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); 000012 2100 MOVS r1,#0 000014 2001 MOVS r0,#1 000016 0540 LSLS r0,r0,#21 000018 f7fffffe BL RCC_APB1PeriphResetCmd 00001c e008 B |L1.48| |L1.30| ;;;156 } ;;;157 else ;;;158 { ;;;159 /* Enable I2C2 reset state */ ;;;160 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); 00001e 2101 MOVS r1,#1 000020 0588 LSLS r0,r1,#22 000022 f7fffffe BL RCC_APB1PeriphResetCmd ;;;161 /* Release I2C2 from reset state */ ;;;162 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); 000026 2100 MOVS r1,#0 000028 2001 MOVS r0,#1 00002a 0580 LSLS r0,r0,#22 00002c f7fffffe BL RCC_APB1PeriphResetCmd |L1.48| ;;;163 } ;;;164 } 000030 bd10 POP {r4,pc} ;;;165 ENDP I2C_Init PROC ;;;173 */ ;;;174 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) 000032 b510 PUSH {r4,lr} ;;;175 { 000034 460a MOV r2,r1 ;;;176 uint32_t tmpreg = 0; 000036 2100 MOVS r1,#0 ;;;177 ;;;178 /* Check the parameters */ ;;;179 assert_param(IS_I2C_ALL_PERIPH(I2Cx)); ;;;180 assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter)); ;;;181 assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter)); ;;;182 assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); ;;;183 assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); ;;;184 assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack)); ;;;185 assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); ;;;186 ;;;187 /* Disable I2Cx Peripheral */ ;;;188 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); 000038 6803 LDR r3,[r0,#0] 00003a 085b LSRS r3,r3,#1 00003c 005b LSLS r3,r3,#1 00003e 6003 STR r3,[r0,#0] ;;;189 ;;;190 /*---------------------------- I2Cx FILTERS Configuration ------------------*/ ;;;191 /* Get the I2Cx CR1 value */ ;;;192 tmpreg = I2Cx->CR1; 000040 6801 LDR r1,[r0,#0] ;;;193 /* Clear I2Cx CR1 register */ ;;;194 tmpreg &= CR1_CLEAR_MASK; 000042 4beb LDR r3,|L1.1008| 000044 4019 ANDS r1,r1,r3 ;;;195 /* Configure I2Cx: analog and digital filter */ ;;;196 /* Set ANFOFF bit according to I2C_AnalogFilter value */ ;;;197 /* Set DFN bits according to I2C_DigitalFilter value */ ;;;198 tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8); 000046 6894 LDR r4,[r2,#8] 000048 0224 LSLS r4,r4,#8 00004a 6853 LDR r3,[r2,#4] 00004c 4323 ORRS r3,r3,r4 00004e 4319 ORRS r1,r1,r3 ;;;199 ;;;200 /* Write to I2Cx CR1 */ ;;;201 I2Cx->CR1 = tmpreg; 000050 6001 STR r1,[r0,#0] ;;;202 ;;;203 /*---------------------------- I2Cx TIMING Configuration -------------------*/ ;;;204 /* Configure I2Cx: Timing */ ;;;205 /* Set TIMINGR bits according to I2C_Timing */ ;;;206 /* Write to I2Cx TIMING */ ;;;207 I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK; 000052 240f MOVS r4,#0xf 000054 0624 LSLS r4,r4,#24 000056 6813 LDR r3,[r2,#0] 000058 43a3 BICS r3,r3,r4 00005a 6103 STR r3,[r0,#0x10] ;;;208 ;;;209 /* Enable I2Cx Peripheral */ ;;;210 I2Cx->CR1 |= I2C_CR1_PE; 00005c 6803 LDR r3,[r0,#0] 00005e 2401 MOVS r4,#1 000060 4323 ORRS r3,r3,r4 000062 6003 STR r3,[r0,#0] ;;;211 ;;;212 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ ;;;213 /* Clear tmpreg local variable */ ;;;214 tmpreg = 0; 000064 2100 MOVS r1,#0 ;;;215 /* Clear OAR1 register */ ;;;216 I2Cx->OAR1 = (uint32_t)tmpreg; 000066 6081 STR r1,[r0,#8] ;;;217 /* Clear OAR2 register */ ;;;218 I2Cx->OAR2 = (uint32_t)tmpreg; 000068 60c1 STR r1,[r0,#0xc] ;;;219 /* Configure I2Cx: Own Address1 and acknowledged address */ ;;;220 /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */ ;;;221 /* Set OA1 bits according to I2C_OwnAddress1 value */ ;;;222 tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \ 00006a 6914 LDR r4,[r2,#0x10] 00006c 6993 LDR r3,[r2,#0x18] 00006e 4323 ORRS r3,r3,r4 000070 4619 MOV r1,r3 ;;;223 (uint32_t)I2C_InitStruct->I2C_OwnAddress1); ;;;224 /* Write to I2Cx OAR1 */ ;;;225 I2Cx->OAR1 = tmpreg; 000072 6081 STR r1,[r0,#8] ;;;226 /* Enable Own Address1 acknowledgement */ ;;;227 I2Cx->OAR1 |= I2C_OAR1_OA1EN; 000074 6883 LDR r3,[r0,#8] 000076 2401 MOVS r4,#1 000078 03e4 LSLS r4,r4,#15 00007a 4323 ORRS r3,r3,r4 00007c 6083 STR r3,[r0,#8] ;;;228 ;;;229 /*---------------------------- I2Cx MODE Configuration ---------------------*/ ;;;230 /* Configure I2Cx: mode */ ;;;231 /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */ ;;;232 tmpreg = I2C_InitStruct->I2C_Mode; 00007e 68d1 LDR r1,[r2,#0xc] ;;;233 /* Write to I2Cx CR1 */ ;;;234 I2Cx->CR1 |= tmpreg; 000080 6803 LDR r3,[r0,#0] 000082 430b ORRS r3,r3,r1 000084 6003 STR r3,[r0,#0] ;;;235 ;;;236 /*---------------------------- I2Cx ACK Configuration ----------------------*/ ;;;237 /* Get the I2Cx CR2 value */ ;;;238 tmpreg = I2Cx->CR2; 000086 6841 LDR r1,[r0,#4] ;;;239 /* Clear I2Cx CR2 register */ ;;;240 tmpreg &= CR2_CLEAR_MASK; 000088 4bda LDR r3,|L1.1012| 00008a 4019 ANDS r1,r1,r3 ;;;241 /* C