实例 1：8 位二进制异步计数器 VHDL 程序。
LIBRARY IEEE;�
USE IEEE.STD_LOGIC_1164.ALL;�
USE IEEE.STD_LOGIC_ARITH.ALL;�
USE IEEE.STD_LOGIC_UNSIGNED.ALL;�
ENTITY dffr IS
PORT (clk: IN STD_LOGIC;
clr: IN STD_LOGIC;
d: IN STD_LOGIC;
q: OUT STD_LOGIC;
qb: OUT STD_LOGIC);
END ENTITY dffr;
ARCHITECTURE ar1 OF dffr IS
SIGNAL si1: STD_LOGIC;
BEGIN
qb<=NOT si1;
q<=si1;
PROCESS(clk，clr)IS
BEGIN
IF(clk='1')THEN
si1<='0';
ELSIF(clk'EVENT AND clk='1')THEN
si1<=d;
END IF;
END PROCESS;
END ARCHITECTURE ar1;
LIBRARY IEEE;�
USE IEEE.STD_LOGIC_1164.ALL;�
USE IEEE.STD_LOGIC_ARITH.ALL;�
USE IEEE.STD_LOGIC_UNSIGNED.ALL;�
ENTITY rplcont IS�
PORT(clk: IN STD_LOGIC;
clr: IN STD_LOGIC;
count: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY rplcont;
ARCHITECTURE ar2 OF rplcont IS
SIGNAL si2: STD_LOGIC_VECTOR(8 DOWNTO 0);
COMPONENT dffr IS
PORT (clk: IN STD_LOGIC;
clr: IN STD_LOGIC;
d: IN STD_LOGIC;
q: OUT STD_LOGIC;
qb: OUT STD_LOGIC);
END COMPONENT dffr;
BEGIN
si2(0)<=clk;
g1: FOR i IN 0 TO 7 GENERATE
C1: dffr PORT MAP(clk=>si2(i)，clr=>clr，d=>si2(i+1)，q=>count(i)，qb=>si2(i+1));
END GENERATE g1;
END ARCHITECTURE ar2;
