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**串行配置（EPCS）设备** 在现代电子系统中，配置存储器是不可或缺的一部分，它用于存储设备的初始化配置数据。EPCS（Electronic Programmable Configuration System）是一种高速、低功耗的串行配置接口标准，广泛应用于FPGA（Field-Programmable Gate Array）和其他可编程逻辑器件。本文将深入探讨EPCS设备及其在选择过程中的关键知识点。 **EPCS接口标准** EPCS是Xilinx公司提出的配置解决方案，它提供了比传统的SPI或JTAG更快的配置速度。EPCS接口基于LVDS（Low-Voltage Differential Signaling）技术，能够实现高速数据传输，从而显著缩短系统启动时间。这种接口设计还支持热插拔和在线编程，使得设备在运行时可以更新配置，提高了系统的灵活性和可靠性。 **EPCS闪存选择指南** 选择合适的EPCS闪存对于优化系统性能至关重要。以下是一些主要考虑因素： 1. **容量**：根据FPGA的配置大小选择合适的EPCS闪存容量。FPGA的配置数据量决定了所需存储空间，确保闪存容量足够存储所有配置数据。 2. **速度**：评估系统启动时间和更新要求，选择具有足够高速传输速率的EPCS闪存。更高的数据传输速率意味着更快的配置时间，这对于实时应用尤其重要。 3. **电源管理**：考虑到功耗，选择低功耗的EPCS闪存，特别是在电池供电或能源敏感的应用中。 4. **兼容性**：确保所选EPCS闪存与目标FPGA芯片兼容。不同的FPGA厂商可能支持不同的EPCS标准版本，如EPCS4、EPCS16等，需要确认它们之间的兼容性。 5. **可靠性**：考虑闪存的耐久性和错误校验机制。EPCS闪存通常具有 ECC（Error Correction Code）功能，以检测并纠正数据传输过程中的错误。 6. **封装和尺寸**：根据PCB布局和空间限制选择合适的封装形式，如SOIC、QFN等。 **EPCS工作流程** EPCS配置流程包括以下几个步骤： 1. **初始化**：系统上电后，FPGA通过EPCS接口与配置设备建立通信。 2. **身份验证**：FPGA检查EPCS闪存中的安全ID，确保配置数据的合法性。 3. **配置加载**：FPGA从EPCS闪存中读取并加载配置数据。 4. **配置检查**：加载完成后，FPGA执行完整性检查，验证配置数据是否正确。 5. **系统运行**：配置成功后，FPGA进入工作模式。 6. **在线更新**：如果需要，可以通过EPCS接口进行在线配置更新。 **总结** EPCS作为一种高效的配置方案，为FPGA系统带来了快速配置、低功耗和高可靠性等优点。在实际应用中，正确选择和使用EPCS设备至关重要。通过理解EPCS接口标准、考虑各种选择因素以及熟悉其工作流程，设计师可以优化系统性能，实现更高效、可靠的FPGA配置。在“Serial Configuration (EPCS) Devices.pdf”文档中，通常会详细阐述这些知识点，提供具体的选型指导和配置示例，为设计者提供实用的参考。

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Serial Configuration (EPCS) Devices.rar （1个子文件）

Serial Configuration (EPCS) Devices.pdf 949KB

January 2014 Altera Corporation

C51014-5.0 Datasheet

QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark

Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their

respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor

products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use

of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are

advised to obtain the latest version of device specifications before relying on any published information and before placing orders

for products or services.

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Feedback Subscribe

ISO

9001:2008

Registered

Serial Configuration (EPCS) Devices

Datasheet

This datasheet describes serial configuration (EPCS) devices.

Supported Devices

Table 1 lists the supported Altera



EPCS devices.

f For more information about programming EPCS devices using the Altera

Programming Unit (APU) or Master Programming Unit (MPU), refer to the Altera

Programming Hardware Datasheet.

f The EPCS device can be re-programmed in system with ByteBlaster



II download

cable or an external microprocessor using SRunner. For more information, refer to

AN418: SRunner: An Embedded Solution for Serial Configuration Device Programming.

Features

EPCS devices offer the following features:

■ Supports active serial (AS) x1 configuration scheme

■ Easy-to-use four-pin interface

■ Low cost, low pin count, and non-volatile memory

■ Low current during configuration and near-zero standby mode current

■ 2.7-V to 3.6-V operation

■ EPCS1, EPCS4, and EPCS16 devices available in 8-pin small-outline integrated

circuit (SOIC) package

■ EPCS64 and EPCS128 devices available in 16-pin SOIC package

Table 1. Altera EPCS Devices

Device

Memory Size

(bits)

On-Chip

Decompression

Support

ISP Support

Cascading

Support

Reprogrammable

Recommended

Operating

Voltage (V)

EPCS1 1,048,576 No Yes No Yes 3.3

EPCS4 4,194,304 No Yes No Yes 3.3

EPCS16 16,777,216 No Yes No Yes 3.3

EPCS64 67,108,864 No Yes No Yes 3.3

EPCS128 134,217,728 No Yes No Yes 3.3

Page 2 Functional Description

Serial Configuration (EPCS) Devices Datasheet January 2014 Altera Corporation

■ Enables the Nios



processor to access unused flash memory through AS memory

interface

■ Reprogrammable memory with more than 100,000 erase or program cycles

■ Write protection support for memory sectors using status register bits

■ In-system programming (ISP) support with SRunner software driver

■ ISP support with USB-Blaster



, EthernetBlaster, or ByteBlaster II download cables

■ Additional programming support with the APU and programming hardware

from BP Microsystems, System General, and other vendors

■ By default, the memory array is erased and the bits are set to

Functional Description

To configure a system using an SRAM-based device, each time you power on the

device, you must load the configuration data. The EPCS device is a flash memory

device that can store configuration data that you use for FPGA configuration purpose

after power on. You can use the EPCS device on all FPGA that support AS x1

configuration scheme.

For an 8-pin SOIC package, you can migrate vertically from the EPCS1 device to the

EPCS4 or EPCS16 device. For a 16-pin SOIC package, you can migrate vertically from

the EPCS64 device to the EPCS128 device.

With the new data decompression feature supported, you can determine using which

EPCS device to store the configuration data for configuring your FPGA.

Example 1 shows how you can calculate the compression ratio to determine which

EPCS device is suitable for the FPGA.

f For more information about the FPGA decompression feature, refer to the

configuration chapter in the appropriate device handbook.

Example 1. Compression Ratio Calculation

EP4SGX530 = 189,000,000 bits

EPCS128 = 134,217,728 bits

Preliminary data indicates that compression typically reduces the

configuration bitstream size by 35% to 55%. Assume worst case that is 35%

decompression.

189,000,000 bits x 0.65 = 122,850,000 bits

The EPCS128 device is suitable.

Active Serial FPGA Configuration Page 3

Serial Configuration (EPCS) Devices DatasheetJanuary 2014 Altera Corporation

Figure 1 shows the EPCS device block diagram.

Accessing Memory in EPCS Devices

You can access the unused memory locations of the EPCS device to store or retrieve

data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for

creating bus-based (especially microprocessor-based) systems in Altera devices.

SOPC Builder assembles library components such as processors and memories into

custom microprocessor systems.

SOPC Builder includes the EPCS device controller core, which is an interface core

designed specifically to work with the EPCS device. With this core, you can create a

system with a Nios embedded processor that allows software access to any memory

location within the EPCS device.

Active Serial FPGA Configuration

The following Altera FPGAs support the AS configuration scheme with EPCS devices:

■ Arria



series

■ Cyclone



series

■ All device families in the Stratix



series except the Stratix device family

There are four signals on the EPCS device that interface directly with the FPGA’s

control signals. The EPCS device signals are

DATA

DCLK

ASDI

, and

nCS

interface with

the

DATA0

DCLK

ASDO

, and

nCSO

control signals on the FPGA, respectively.

1 For more information about the EPCS device pin description, refer to Table 23 on

page 36.

Figure 1. EPCS Device Block Diagram

Control

Logic

I/O Shift

Memory

Array

Status RegisterAddress Counter

Decode Logic

Data Buffer

nCS

DCLK

DATA

ASDI

EPCS Device

Page 4 Active Serial FPGA Configuration

Serial Configuration (EPCS) Devices Datasheet January 2014 Altera Corporation

Figure 2 shows the configuration of an FPGA device in the AS configuration scheme

with an EPCS device using a download cable.

Figure 2. Altera FPGA Configuration in AS Mode Using a Download Cable

(1),

(4)

Notes to Figure 2:

(1) For more information about the V

value, refer to the configuration chapter in the appropriate device handbook.

(2) EPCS devices cannot be cascaded.

(3) Connect the

MSEL[]

input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate

device handbook.

(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration

chapter in the appropriate device handbook.

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

nCE

nCONFIG

nSTATUS

MSEL[]

nCEO

CONF_DONE

ASDO

(1) V

(1)

10 kΩ 10 kΩ 10 kΩ

10 kΩ

(3)

Altera FPGA

EPCS Device (2)

Pin 1

N.C.

Active Serial FPGA Configuration Page 5

Serial Configuration (EPCS) Devices DatasheetJanuary 2014 Altera Corporation

Figure 3 shows the configuration of an FPGA device in the AS configuration scheme

with an EPCS device using the APU or a third-party programmer.

In an AS configuration, the FPGA acts as the configuration master in the

configuration flow and provides the clock to the EPCS device. The FPGA enables the

EPCS device by pulling the

nCS

signal low using the

nCSO

signal as shown in Figure 2

and Figure 3. Then, the FPGA sends the instructions and addresses to the EPCS device

using the

ASDO

signal. The EPCS device responds to the instructions by sending the

configuration data to the FPGA’s

DATA0

pin on the falling edge of

DCLK

. The data is

latched into the FPGA on the next

DCLK

signal’s falling edge.

1 Before the FPGA enters configuration mode, ensure that V

of the EPCS device is

ready. If V

is not ready, you must hold

nCONFIG

low until all power rails of EPCS

device are ready.

The FPGA controls the

nSTATUS

and

CONF_DONE

pins during configuration in the AS

mode. If the

CONF_DONE

signal does not go high at the end of configuration, or if the

signal goes high too early, the FPGA pulses its

nSTATUS

pin low to start a

reconfiguration. If the configuration is successful, the FPGA releases the

CONF_DONE

pin, allowing the external 10-k resistor to pull the

CONF_DONE

signal high. The FPGA

initialization begins after the

CONF_DONE

pin goes high. After the initialization, the

FPGA enters user mode.

f For more information about configuring the FPGAs in AS configuration mode or

other configuration modes, refer to the configuration chapter in the appropriate

device handbook.

Figure 3. Altera FPGA Configuration in AS Mode Using APU or a Third-party Programmer

(1),

(4)

Notes to Figure 3:

(1) For more information about the V

value, refer to the configuration chapter in the appropriate device handbook.

(2) EPCS devices cannot be cascaded.

(3) Connect the

MSEL[]

input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate

device handbook.

(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration

chapter in the appropriate device handbook.

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

nCE

nCONFIG

nSTATUS

MSEL[]

nCEO

CONF_DONE

ASDO

(1) V

(1)

10 kΩ 10 kΩ 10 kΩ

(3)

Altera FPGA

EPCS Device (2)

N.C.

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