PCI EXPRESS BASE SPECIFICATION, REV. 3.1
5
Update Ordering and Granularity Observed by a Read Transaction ................ 145 2.4.2.
Update Ordering and Granularity Provided by a Write Transaction ................ 146 2.4.3.
2.5. VIRTUAL CHANNEL (VC) MECHANISM ........................................................................ 147
Virtual Channel Identification (VC ID) .............................................................. 149 2.5.1.
TC to VC Mapping .............................................................................................. 150 2.5.2.
VC and TC Rules ................................................................................................. 151 2.5.3.
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 152
Flow Control Rules ............................................................................................. 153 2.6.1.
2.7. DATA INTEGRITY ......................................................................................................... 164
ECRC Rules ........................................................................................................ 164 2.7.1.
Error Forwarding ............................................................................................... 168 2.7.2.
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 170
2.9. LINK STATUS DEPENDENCIES ...................................................................................... 171
Transaction Layer Behavior in DL_Down Status ............................................... 171 2.9.1.
Transaction Layer Behavior in DL_Up Status ................................................... 172 2.9.2.
Transaction Layer Behavior During Downstream Port Containment ............... 173 2.9.3.
3. DATA LINK LAYER SPECIFICATION ...................................................................... 175
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 175
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 177
Data Link Control and Management State Machine Rules ................................ 178 3.2.1.
3.3.
FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 180
Flow Control Initialization State Machine Rules ............................................... 181 3.3.1.
3.4. DATA LINK LAYER PACKETS (DLLPS) ........................................................................ 184
Data Link Layer Packet Rules ............................................................................ 184 3.4.1.
3.5. DATA INTEGRITY ......................................................................................................... 189
Introduction......................................................................................................... 189 3.5.1.
LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 189 3.5.2.
LCRC and Sequence Number (TLP Receiver) .................................................... 202 3.5.3.
4. PHYSICAL LAYER SPECIFICATION ........................................................................ 211
4.1. INTRODUCTION ............................................................................................................ 211
4.2. LOGICAL SUB-BLOCK ................................................................................................... 211
Encoding for 2.5 GT/s and 5.0 GT/s Data Rates ................................................ 212 4.2.1.
Encoding for 8.0 GT/s and Higher Data Rates................................................... 220 4.2.2.
Link Equalization Procedure for 8.0 GT/s Data Rate ........................................ 238 4.2.3.
Link Initialization and Training .......................................................................... 245 4.2.4.
Link Training and Status State Machine (LTSSM) Descriptions ........................ 264 4.2.5.
Link Training and Status State Rules .................................................................. 267 4.2.6.
Clock Tolerance Compensation .......................................................................... 332 4.2.7.
Compliance Pattern in 8b/10b Encoding ............................................................ 337 4.2.8.
Modified Compliance Pattern in 8b/10b Encoding ............................................ 338 4.2.9.
Compliance Pattern in 128b/130b Encoding ...................................................... 340 4.2.10.
Modified Compliance Pattern in 128b/130b Encoding ...................................... 342 4.2.11.
4.3. ELECTRICAL SUB-BLOCK ............................................................................................. 343
Electrical Specification Organization................................................................. 343 4.3.1.
Interoperability Criteria for 2.5, 5.0, and 8.0 GT/s Devices .............................. 343 4.3.2.
