3
AFE5816
www.ti.com.cn
ZHCSDT7E –APRIL 2015–REVISED SEPTEMBER 2017
版权 © 2015–2017, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 3
5 说说明明 （（续续））.............................................................. 4
6 Device Family Comparison Table ........................ 6
7 Pin Configuration and Functions......................... 7
8 Specifications....................................................... 11
8.1 Absolute Maximum Ratings .................................... 11
8.2 ESD Ratings............................................................ 11
8.3 Recommended Operating Conditions..................... 11
8.4 Thermal Information................................................ 13
8.5 Electrical Characteristics: TGC Mode..................... 13
8.6 Electrical Characteristics: CW Mode....................... 16
8.7 Digital Characteristics ............................................. 17
8.8 Output Interface Timing Requirements................... 18
8.9 Serial Interface Timing Requirements..................... 19
8.10 Typical Characteristics: TGC Mode ...................... 20
8.11 Typical Characteristics: CW Mode........................ 28
9 Detailed Description............................................ 29
9.1 Overview ................................................................. 29
9.2 Functional Block Diagram ....................................... 30
9.3 Feature Description................................................. 31
9.4 Device Functional Modes........................................ 74
9.5 Programming........................................................... 79
10 Application and Implementation........................ 81
10.1 Application Information.......................................... 81
10.2 Typical Application ................................................ 81
10.3 Do's and Don'ts..................................................... 85
10.4 Initialization Set Up ............................................... 85
11 Power Supply Recommendations ..................... 86
11.1 Power Sequencing and Initialization..................... 86
12 Layout................................................................... 87
12.1 Layout Guidelines ................................................. 87
12.2 Layout Example .................................................... 88
13 Register Maps...................................................... 95
13.1 Serial Register Map .............................................. 95
14 器器件件和和文文档档支支持持 ................................................... 159
14.1 文档支持 ............................................................. 159
14.2 社区资源.............................................................. 159
14.3 商标 ..................................................................... 159
14.4 静电放电警告....................................................... 159
14.5 Glossary.............................................................. 159
15 机机械械、、封封装装和和可可订订购购信信息息..................................... 159
4 修修订订历历史史记记录录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (November 2015) to Revision E Page
• Deleted Output and Gain Code Step Response vs Time figure........................................................................................... 25
• Deleted condition statement from Output and Gain Code Step Response vs Time figure.................................................. 25
• Changed Device Power vs Gain Code figure....................................................................................................................... 26
• Deleted Device Power vs Gain Code (TGC_CONS register bit = 1) figure ......................................................................... 26
• Changed VCA Power vs Gain Code figure .......................................................................................................................... 26
• Changed AVDD_1P9 Supply Current vs Gain Code figure.................................................................................................. 27
• Deleted contour curves from Typical Characteristics: TGC Mode section........................................................................... 27
• Changed Input Signal Support in TGC Mode section .......................................................................................................... 33
• Added footnote 2 to Profile Description for Up, Down Ramp Mode table ........................................................................... 40
• Changed TGC_SLOPE and TGC_UP_DN clock traces in External Non-Uniform Mode figure........................................... 41
• Added footnote 2 to Profile Description for External Non-Uniform Mode table ................................................................... 42
• Changed Figure 72 .............................................................................................................................................................. 46
• Added footnote 2 to Internal Non-Uniform Mode Profile Definition table ............................................................................ 48
• Added Latency Between a Transition in TGC_SLOPE and the Resulting Change in Gain table and associated
paragraph to Timing Specifications section.......................................................................................................................... 48
• Changed second sentence in sixth paragraph of Continuous-Wave (CW) Beamformer section ....................................... 52
• Changed Figure 77 .............................................................................................................................................................. 53
• Changed last paragraph of 16 × ƒ
cw
Mode section ............................................................................................................. 54
• Changed Clock Configurations figure .................................................................................................................................. 57
• Changed Number of samples from "2045" to "2047" in Table 15 ........................................................................................ 68
• Changed HPF_ROUND_ENABLE register bit (register 21, bit 5) to HPF_ROUND_EN_CH1-8 and
HPF_ROUND_EN_CH9-16 bits in last paragraph of Digital HPF section ........................................................................... 70
评论0
最新资源