SLVS-EC_specification_V1_2.pdf_slvs接口资源-CSDN文库

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从给定的文件信息中，我们可以提炼出以下关于SONY SLVS-EC接口协议规范的知识点： SLVS-EC（Serializer Low Voltage Signaling - Embedded Clock）接口协议是由索尼公司开发的一种串行视频接口标准。该接口技术旨在提供高带宽、低功耗和高数据传输稳定性的解决方案。SLVS-EC的设计特别适合用于高分辨率和高帧率的图像传感器。 SLVS-EC接口具备如下特点： 1. 高带宽：通过串行传输，SLVS-EC可以提供较高的数据传输速率，这对于现代高分辨率摄像应用非常关键。 2. 低功耗：与传统的并行接口相比，串行接口可以通过降低信号线的数量来减少功耗，这对于移动设备和需要节能的应用场景非常重要。 3. 低冗余度的组包方式：SLVS-EC接口采用了一种高效的组包机制，减少了数据传输中的冗余信息，进而提高了数据传输的效率。 4. 稳定性与可靠性：SLVS-EC提供了更加可靠和稳定的信号传输能力，减少了数据丢失或错误的可能性。文件还提到用户在考虑或已经使用具备SLVS-EC接口的CMOS图像传感器或数字信号处理器（DSP）产品时，必须遵守“用户限制通告”（USER RESTRICTION NOTICE）。这个通告可能会由索尼公司或其子公司、分销商随时修改，并且用户需要遵循通告的最新版本。索尼保留修改这个通告的权利，并且要求用户在使用SLVS-EC接口产品时，必须获得索尼授权代表的咨询意见。此外，文件中声明了索尼公司不对用户使用本规范书中技术信息所带来的任何问题或第三方权利的侵犯承担责任。用户必须自行解决这些问题和侵权行为。此外，本规范文件以“现状”提供，不附带任何形式的保证，索尼明确声明放弃所有明示或暗示的保证，包括但不限于适销性、特定用途的适用性保证，以及不侵犯任何第三方知识产权的保证。索尼也不保证本规范书中显示的技术信息会满足用户的要求。以上内容概述了SLVS-EC接口协议的规范文件所包含的要点，以及用户在使用SLVS-EC接口产品时需要遵守的法律和版权规定。在实际应用中，用户应确保遵守索尼公司的相关规定，以免引起法律纠纷。同时，用户应注意到，使用SLVS-EC接口技术的数据传输和系统集成需要考虑到该协议的这些限制和特性。

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Sony Corporation

SLVS-EC Specification

1／74

Sony Confidential

SLVS-EC

Specification

Version 1.2 xx July 2013

Sony Corporation

SLVS-EC Specification

2／74

Sony Confidential

USE RESTRICTION NOTICE

This USE RESTRICTION NOTICE (“Notice”) is for customers who are considering or currently

using the CMOS image sensor products or the DSP products (“Products”) integrated with SLVS-EC

interface set forth in this specification. Sony Corporation (“Sony”) may, at any time, modify this

Notice which will be available to you in the latest specification for SLVS-EC. You should abide by

the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice

on the Products, such a use restriction notice will additionally apply between you and the subsidiary

or distributor. You should consult a sales representative of the subsidiary or distributor of Sony

(“Sales Representative”) on such a use restriction notice when you consider using the Products with

SLVS-EC interface.

All materials contained herein are protected by copyright laws, and may not be reproduced,

republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner

without the permission of Sony.

Disclaimer

Sony will not assume responsibility for any problems in connection with your use of the technical

information shown in this specification or for any infringement of third-party rights due to the same.

It is therefore your sole legal and financial responsibility to resolve any such problems and

infringement. THIS SPECIFICATION DOCUMENT IS PROVIDED "AS IS" AND WITHOUT

WARRANTY OF ANY KIND, AND SONY EXPRESSLY DISCLAIMS ALL WARRANTIES,

EXPRESS OR IMPLIED, STATUTORY OR OTHERWISE, INCLUDING, BUT NOT LIMITED

TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

PARTICULAR USE OR PURPOSE, AND THE WARRANTY OF NON-INFRINGEMENT OF

ANY THIRD PARTY INTELLECTUAL PROPERTY. SONY DOES NOT WARRANT THAT THE

TECHNICAL INFORMATION SHOWN IN THIS SPECIFICATION WILL MEET YOUR

REQUIREMENTS. FURTHERMORE, SONY DOES NOT WARRANT OR MAKE ANY

REPRESENTATIONS REGARDING THE USE OR THE RESULTS OF THE USE OF THE

TECHNICAL INFORMATION SHOWN IN THIS SPECIFICATION IN TERMS OF ITS

CORRECTNESS, ACCURACY, RELIABILITY, CONNECTIVITY OR OTHERWISE. NO ORAL

OR WRITTEN INFORMATION OR ADVICE GIVEN BY SONY OR A SONY AUTHORIZED

REPRESENTATIVE OR SALES REPRESENTATIVE SHALL CREATE A WARRANTY OR IN

ANY WAY INCREASE THE SCOPE OF THIS WARRANTY.

No License Implied

The technical information shown in this specification is for your reference purposes only. The

availability of this specification shall not be construed as giving any indication that Sony and its

licensors will license any intellectual property rights in such information by any implication or

otherwise.

Governing Law

This Notice shall be governed by and construed in accordance with the laws of Japan, without

reference to principles of conflict of laws or choice of laws. All controversies and disputes arising

out of or relating to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District

Court in Japan as the court of first instance.

Other Applicable Terms and Conditions

The terms and conditions set forth in the Sony specifications, which will be made available to you

when you order the Products, shall apply to your use of the Products instead of this specification.

You should review those terms and conditions when you consider purchasing and/or using the

Products.

Sony Corporation

SLVS-EC Specification

4／74

Sony Confidential

CONTENTS

1. Overview ...................................................................................................................................... 8

1.1. Scope ..................................................................................................................................... 8

1.2. Purpose .................................................................................................................................. 8

2. Reference Documents ................................................................................................................. 9

3. Definitions, acronyms, and abbreviations ................................................................................. 9

3.1. Definitions ............................................................................................................................ 9

3.2. Acronyms and abbreviations ................................................................................................. 9

4. Architecture ............................................................................................................................... 10

4.1. System Topology ................................................................................................................. 10

4.1.1. Basic Topology ........................................................................................................... 10

4.1.2. Multiple I/F Topology ................................................................................................. 11

4.1.3. Multiple CIS Topology ............................................................................................... 12

4.2. Frame Synchronization Scheme .......................................................................................... 13

4.2.1. DSP Master with shared clock .................................................................................... 13

4.2.2. DSP Master without shared clock ............................................................................... 13

4.2.3. CIS Master with shared clock ..................................................................................... 14

4.2.4. CIS Master without shared clock ................................................................................ 15

4.3. Hierarchical Structure ......................................................................................................... 16

4.3.1. Application Layer ....................................................................................................... 17

4.3.2. LINK Layer ................................................................................................................. 17

4.3.3. PHY Layer .................................................................................................................. 17

5. Application Layer Protocol Interface ...................................................................................... 18

5.1. RAW Pixel Data Format ..................................................................................................... 18

5.2. Embedded Data Transfer ..................................................................................................... 18

5.3. Frame Format ...................................................................................................................... 19

5.3.1. Single Stream Frame Format ...................................................................................... 19

5.3.2. Initialization ................................................................................................................ 20

5.3.3. Standby ....................................................................................................................... 21

5.3.4. Mode Change .............................................................................................................. 22

5.3.5. Mode Change with Standby ........................................................................................ 25

5.3.6. Interrupt....................................................................................................................... 26

5.4. Attribute and Configuration Register .................................................................................. 27

5.5. Multiple Stream Transfer .................................................................................................... 28

5.5.1. Frame Format of Multiple Stream Transfer ................................................................ 29

6. LINK Layer Specification ........................................................................................................ 30

6.1. Pixel to Byte Format Converter .......................................................................................... 30

6.1.1. Payload Data Format ................................................................................................... 34

6.2. Payload Data Error Correction ............................................................................................ 36

6.2.1. Payload Data Format with ECC .................................................................................. 37

6.3. Packetize ............................................................................................................................. 38

6.3.1. Packet Format ............................................................................................................. 38

6.3.2. Format and Protocol Error Handling ........................................................................... 40

6.4. Lane Management ............................................................................................................... 41

6.4.1. Lane Distribution ........................................................................................................ 42

6.4.2. Lane Distribution with Payload ECC .......................................................................... 43

6.5. LINK Protocol Management ............................................................................................... 44

Sony Corporation

SLVS-EC Specification

5／74

Sony Confidential

6.5.1. Packet Header Generation ........................................................................................... 44

6.5.2. Packet Footer Generation ............................................................................................ 46

6.5.3. Protocol Management FSM ........................................................................................ 48

7. PHY Layer Specification .......................................................................................................... 51

7.1. PHY Protocol Management ................................................................................................ 51

7.1.1. Protocol Management FSM ........................................................................................ 51

7.1.2. Training Sequence ....................................................................................................... 52

7.1.3. Packet Data Transfer Sequence ................................................................................... 53

7.1.4. Standby Sequence ....................................................................................................... 53

7.1.5. PHY Control Code ...................................................................................................... 54

7.2. Bandwidth Control .............................................................................................................. 54

7.3. Lane Skew Control ............................................................................................................. 56

7.4. Symbol Encoding ................................................................................................................ 57

7.5. Bit Ordering in Symbol Data .............................................................................................. 59

7.6. Symbol Alignment .............................................................................................................. 60

7.7. Baud Rate Scheme .............................................................................................................. 60

8. Electrical Characteristics ......................................................................................................... 61

8.1. TX Characteristics .............................................................................................................. 61

8.2. RX Characteristics .............................................................................................................. 62

8.3. Common Characteristics ..................................................................................................... 63

8.4. Interconnect Characteristics ................................................................................................ 64

Annex A. RX Analog Functional Specification ............................................................................... 65

Annex B. Implementation of Multiple Stream Transfer (Informative) ........................................ 70

Annex C. Frame format depending on CIS implementation ........................................................ 72

Annex D. RX Protocol Management FSM (Informative) .............................................................. 73

FIGURES

Figure 1 Basic Topology .................................................................................................................. 10

Figure 2 Multiple I/F Topology ....................................................................................................... 11

Figure 3 Multiple CIS Topology ...................................................................................................... 12

Figure 4 DSP Master with shared clock ........................................................................................... 13

Figure 5 DSP Master without shared clock ...................................................................................... 14

Figure 6 CIS Master with shared clock ............................................................................................ 15

Figure 7 CIS Master without shared clock ....................................................................................... 15

Figure 8 SLVS-EC Hierarchical Structure ....................................................................................... 16

Figure 9 Example of Single Stream Frame Format.......................................................................... 19

Figure 10 Example Frame Format and Control Sequence for Initialization .................................... 20

Figure 11 Example Frame Format and Control Sequence for Standby ............................................ 21

Figure 12 Example Frame Format and Control Sequence for Mode Change .................................. 22

Figure 13 Example Sequence of Lane Num Change (1 to 4)........................................................... 23

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liujin11110

2024-12-12

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