v
3.4.2. Byte 1: Codeword size ............................................................................................. 97
3.4.3. Byte 2-3: Bad blocks maximum per LUN ................................................................. 97
3.4.4. Byte 4-5: Block endurance ....................................................................................... 97
3.5. Discovery and Initialization.............................................................................................. 97
3.5.1. Discovery without CE_n pin reduction ..................................................................... 97
3.5.2. Discovery with CE_n pin reduction .......................................................................... 98
3.5.3. Target Initialization ................................................................................................. 101
4. Data Interface and Timing .................................................................................................... 102
4.1. Data Interface Type Overview ...................................................................................... 102
4.2. Signal Function Assignment.......................................................................................... 103
4.3. Bus State ....................................................................................................................... 104
4.3.1. SDR........................................................................................................................ 104
4.3.2. NV-DDR ................................................................................................................. 104
4.3.3. NV-DDR2, NV-DDR3 and NV-LPDDR4 ................................................................ 106
4.3.4. Pausing Data Input/Output and Restarting an Exited Data Input/Output Sequence
106
4.4. NV-DDR / NV-DDR2 / NV-DDR3 / NV-LPDDR4 and Repeat Bytes ............................. 110
4.5. Data Interface / Timing Mode Transitions ..................................................................... 111
4.5.1. SDR Transition from NV-DDR or NV-DDR2 .......................................................... 112
4.5.2. NV-DDR2 Recommendations ................................................................................ 112
4.5.3. NV-DDR3 Recommendations ................................................................................ 112
4.5.4. NV-DDR3/NV-LPDDR4 Initialization ...................................................................... 112
4.6. Data Bus Inversion ........................................................................................................ 114
4.6.1. DBI Purpose and Function ..................................................................................... 114
4.6.1. DBI Signal Encoding .............................................................................................. 114
4.7. Test Conditions ............................................................................................................. 114
4.7.1. SDR Only ............................................................................................................... 114
4.7.2. Devices that Support Driver Strength Settings ...................................................... 115
4.8. ZQ Calibration ............................................................................................................... 116
4.8.1. ZQ External Resistor Value, Tolerance, and Capacitive loading .......................... 117
4.9. I/O Drive Strength ......................................................................................................... 118
4.10. Output Slew Rate ...................................................................................................... 120
4.11. Capacitance ............................................................................................................... 125
4.11.1. Legacy Capacitance Requirements ................................................................... 125
4.11.2. Capacitance Requirements (Informative)........................................................... 127
4.11.3. Package Electrical Specifications and Pad Capacitance for Raw NAND Devices
Supporting I/O Speeds Greater than 533MT/s ..................................................................... 128
4.12. Impedance Values ..................................................................................................... 132
4.12.1. NV-DDR ............................................................................................................. 133
4.12.2. NV-DDR2 ........................................................................................................... 135
4.12.3. NV-DDR3 ........................................................................................................... 137
4.12.1. NV-LPDDR4 Pull-Up .......................................................................................... 139
4.13. Output Driver Sensitivity ............................................................................................ 139
4.14. Input Slew Rate Derating .......................................................................................... 140
4.14.1. NV-DDR ............................................................................................................. 140
4.14.2. NV-DDR2/NV-DDR3 .......................................................................................... 140
4.14.3. NV-LPDDR4 ....................................................................................................... 148
4.15. Differential Signaling (NV-DDR2/NV-DDR3/NV-LPDDR4) ....................................... 148
4.16. Warmup Cycles (NV-DDR2/NV-DDR3/NV-LPDDR4) ............................................... 149
4.17. On-die Termination (NV-DDR2/NV-DDR3/NV-LPDDR4) .......................................... 150
4.17.1. ODT Sensitivity ................................................................................................... 154
4.17.2. Self-termination ODT.......................................................................................... 155
4.17.3. Matrix Termination .............................................................................................. 155
4.18. Timing Parameters .................................................................................................... 162
4.18.1. General Parameters ........................................................................................... 163
4.18.2. SDR .................................................................................................................... 167
