Mixed-Signal Modeling/Verification Engineer
Imagine what you could do here at Apple! Together, we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish.
Apple’s growing wireless silicon development team is seeking an exceptional candidate for its modeling and verification team. In this role, you will be modeling and verifying Analog/RF/Mixed-Signal blocks and SOCs using SystemVerilog to create behavioral models, testbenches, checkers, and tests. You will build and execute test plans to meet project schedules and quality requirements.
You will become part of a hands-on development team that fosters engineering excellence, creativity, and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in that type of environment. It's one of the most exciting aspects of the job. Dynamic, smart people and inspiring, innovative technologies are the norm here.
Will you help us design the next generation of revolutionary Apple products?
In this role, core responsibilities include, but are not limited to the following:
•Develop accurate and simulation-efficient analog behavioral models for Analog/RF blocks in SystemVerilog.
• Build and reuse real-numbered analog behavioral models of the Analog and Mixed-Signal Circuits.
•Verify that the behavioral models are accurate representations of corresponding analog circuits.
•Review specifications and collaborate with the design team to extract features, define, and execute models’ development/validation plans.
•Build and reuse monitors and checkers for RF, Mixed-Signal, and Digital blocks.
•Debug failures, fix testbench/model/checker issues, manage bug tracking, etc.
•Write scripts for automation of the flow and improve Mixed-Signal verification methodology.
•Develop top/block-level Mixed-Signal and Digital testbenches and generate directed/ constrained random tests in a UVM framework.
- BS with 10+ years of relevant industrial experience.
- Hands-on experience in Mixed-Signal Verification and Real Numbered Modeling of Mixed-Signal Systems.
- Analog circuit design knowledge and a good understanding of basic analog devices.
- Master’s or Ph.D. with 5+ years of experience in modeling and verification of analog/RF circuits.
- Modeling experience for RF/Mixed-Signal blocks with real-number models in SystemVerilog or a similar HDL.
- In-depth understanding of SystemVerilog, real number models, user-defined nettypes, and Verilog-AMS.
- Deep understanding of AMS and RF blocks like filters, ADC, DAC, VCO, A/D/PLL, Serdes, LNA, Mixer, etc.
- Experience in transistor-level Spice simulations.
- Experience in writing scripts in languages such as Perl or Python.
- Knowledge of signal processing using Python or MATLAB.
- Experience in modeling with SystemC and/or C/C++.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.